/*
+ * Copyright (c) 2013-2014 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2005 The Regents of The University of Michigan
* All rights reserved.
*
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
+ * Mitch Hayenga
*/
/**
* Hardware Prefetcher Definition.
*/
-#include "base/trace.hh"
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/prefetch/base_prefetcher.hh"
-#include "mem/request.hh"
-#include <list>
-
-BasePrefetcher::BasePrefetcher(const BaseCacheParams *p)
- : size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
- serialSquash(p->prefetch_serial_squash),
- cacheCheckPush(p->prefetch_cache_check_push),
- only_data(p->prefetch_data_accesses_only)
+#include "mem/cache/prefetch/base.hh"
+
+#include <cassert>
+
+#include "base/intmath.hh"
+#include "cpu/base.hh"
+#include "mem/cache/base.hh"
+#include "params/BasePrefetcher.hh"
+#include "sim/system.hh"
+
+BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
+ : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
+ masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
+ secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
+ paddress(pkt->req->getPaddr()), cacheMiss(miss)
+{
+ unsigned int req_size = pkt->req->getSize();
+ if (!write && miss) {
+ data = nullptr;
+ } else {
+ data = new uint8_t[req_size];
+ Addr offset = pkt->req->getPaddr() - pkt->getAddr();
+ std::memcpy(data, &(pkt->getConstPtr<uint8_t>()[offset]), req_size);
+ }
+}
+
+BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr)
+ : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC),
+ secure(pfi.secure), size(pfi.size), write(pfi.write),
+ paddress(pfi.paddress), cacheMiss(pfi.cacheMiss), data(nullptr)
+{
+}
+
+void
+BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
+{
+ if (isFill) {
+ parent.notifyFill(pkt);
+ } else {
+ parent.probeNotify(pkt, miss);
+ }
+}
+
+BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
+ : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
+ lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
+ onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
+ masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
+ prefetchOnAccess(p->prefetch_on_access),
+ useVirtualAddresses(p->use_virtual_addresses), issuedPrefetches(0),
+ usefulPrefetches(0), tlb(nullptr)
{
}
void
BasePrefetcher::setCache(BaseCache *_cache)
{
+ assert(!cache);
cache = _cache;
+
+ // If the cache has a different block size from the system's, save it
blkSize = cache->getBlockSize();
+ lBlkSize = floorLog2(blkSize);
}
void
-BasePrefetcher::regStats(const std::string &name)
+BasePrefetcher::regStats()
{
- pfIdentified
- .name(name + ".prefetcher.num_hwpf_identified")
- .desc("number of hwpf identified")
- ;
+ ClockedObject::regStats();
- pfMSHRHit
- .name(name + ".prefetcher.num_hwpf_already_in_mshr")
- .desc("number of hwpf that were already in mshr")
- ;
-
- pfCacheHit
- .name(name + ".prefetcher.num_hwpf_already_in_cache")
- .desc("number of hwpf that were already in the cache")
+ pfIssued
+ .name(name() + ".num_hwpf_issued")
+ .desc("number of hwpf issued")
;
- pfBufferHit
- .name(name + ".prefetcher.num_hwpf_already_in_prefetcher")
- .desc("number of hwpf that were already in the prefetch queue")
- ;
+}
- pfRemovedFull
- .name(name + ".prefetcher.num_hwpf_evicted")
- .desc("number of hwpf removed due to no buffer left")
- ;
+bool
+BasePrefetcher::observeAccess(const PacketPtr &pkt, bool miss) const
+{
+ bool fetch = pkt->req->isInstFetch();
+ bool read = pkt->isRead();
+ bool inv = pkt->isInvalidate();
+
+ if (pkt->req->isUncacheable()) return false;
+ if (fetch && !onInst) return false;
+ if (!fetch && !onData) return false;
+ if (!fetch && read && !onRead) return false;
+ if (!fetch && !read && !onWrite) return false;
+ if (!fetch && !read && inv) return false;
+ if (pkt->cmd == MemCmd::CleanEvict) return false;
+
+ if (onMiss) {
+ return miss;
+ }
- pfRemovedMSHR
- .name(name + ".prefetcher.num_hwpf_removed_MSHR_hit")
- .desc("number of hwpf removed because MSHR allocated")
- ;
+ return true;
+}
- pfIssued
- .name(name + ".prefetcher.num_hwpf_issued")
- .desc("number of hwpf issued")
- ;
+bool
+BasePrefetcher::inCache(Addr addr, bool is_secure) const
+{
+ return cache->inCache(addr, is_secure);
+}
- pfSpanPage
- .name(name + ".prefetcher.num_hwpf_span_page")
- .desc("number of hwpf spanning a virtual page")
- ;
+bool
+BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
+{
+ return cache->inMissQueue(addr, is_secure);
+}
- pfSquashed
- .name(name + ".prefetcher.num_hwpf_squashed_from_miss")
- .desc("number of hwpf that got squashed due to a miss aborting calculation time")
- ;
+bool
+BasePrefetcher::hasBeenPrefetched(Addr addr, bool is_secure) const
+{
+ return cache->hasBeenPrefetched(addr, is_secure);
}
-inline bool
-BasePrefetcher::inCache(Addr addr)
+bool
+BasePrefetcher::samePage(Addr a, Addr b) const
{
- if (cache->inCache(addr)) {
- pfCacheHit++;
- return true;
- }
- return false;
+ return roundDown(a, pageBytes) == roundDown(b, pageBytes);
}
-inline bool
-BasePrefetcher::inMissQueue(Addr addr)
+Addr
+BasePrefetcher::blockAddress(Addr a) const
{
- if (cache->inMissQueue(addr)) {
- pfMSHRHit++;
- return true;
- }
- return false;
+ return a & ~((Addr)blkSize-1);
}
-PacketPtr
-BasePrefetcher::getPacket()
+Addr
+BasePrefetcher::blockIndex(Addr a) const
{
- DPRINTF(HWPrefetch, "%s:Requesting a hw_pf to issue\n", cache->name());
+ return a >> lBlkSize;
+}
- if (pf.empty()) {
- DPRINTF(HWPrefetch, "%s:No HW_PF found\n", cache->name());
- return NULL;
- }
+Addr
+BasePrefetcher::pageAddress(Addr a) const
+{
+ return roundDown(a, pageBytes);
+}
- PacketPtr pkt;
- bool keepTrying = false;
- do {
- pkt = *pf.begin();
- pf.pop_front();
- if (!cacheCheckPush) {
- keepTrying = cache->inCache(pkt->getAddr());
- }
- if (pf.empty()) {
- cache->deassertMemSideBusRequest(BaseCache::Request_PF);
- if (keepTrying) return NULL; //None left, all were in cache
- }
- } while (keepTrying);
+Addr
+BasePrefetcher::pageOffset(Addr a) const
+{
+ return a & (pageBytes - 1);
+}
- pfIssued++;
- return pkt;
+Addr
+BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
+{
+ return page + (blockIndex << lBlkSize);
}
void
-BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time)
+BasePrefetcher::probeNotify(const PacketPtr &pkt, bool miss)
{
- if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && only_data))
- {
- //Calculate the blk address
- Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
-
- //Check if miss is in pfq, if so remove it
- std::list<PacketPtr>::iterator iter = inPrefetch(blkAddr);
- if (iter != pf.end()) {
- DPRINTF(HWPrefetch, "%s:Saw a miss to a queued prefetch, removing it\n", cache->name());
- pfRemovedMSHR++;
- pf.erase(iter);
- if (pf.empty())
- cache->deassertMemSideBusRequest(BaseCache::Request_PF);
- }
-
- //Remove anything in queue with delay older than time
- //since everything is inserted in time order, start from end
- //and work until pf.empty() or time is earlier
- //This is done to emulate Aborting the previous work on a new miss
- //Needed for serial calculators like GHB
- if (serialSquash) {
- iter = pf.end();
- iter--;
- while (!pf.empty() && ((*iter)->time >= time)) {
- pfSquashed++;
- pf.pop_back();
- iter--;
- }
- if (pf.empty())
- cache->deassertMemSideBusRequest(BaseCache::Request_PF);
- }
+ // Don't notify prefetcher on SWPrefetch, cache maintenance
+ // operations or for writes that we are coaslescing.
+ if (pkt->cmd.isSWPrefetch()) return;
+ if (pkt->req->isCacheMaintenance()) return;
+ if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
+ if (!pkt->req->hasPaddr()) {
+ panic("Request must have a physical address");
+ }
+ if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
+ usefulPrefetches += 1;
+ }
- std::list<Addr> addresses;
- std::list<Tick> delays;
- calculatePrefetch(pkt, addresses, delays);
-
- std::list<Addr>::iterator addr = addresses.begin();
- std::list<Tick>::iterator delay = delays.begin();
- while (addr != addresses.end())
- {
- DPRINTF(HWPrefetch, "%s:Found a pf canidate, inserting into prefetch queue\n", cache->name());
- //temp calc this here...
- pfIdentified++;
- //create a prefetch memreq
- Request * prefetchReq = new Request(*addr, blkSize, 0);
- PacketPtr prefetch;
- prefetch = new Packet(prefetchReq, MemCmd::HardPFReq, -1);
- prefetch->allocate();
- prefetch->req->setThreadContext(pkt->req->getCpuNum(),
- pkt->req->getThreadNum());
-
- prefetch->time = time + (*delay); //@todo ADD LATENCY HERE
- //... initialize
-
- //Check if it is already in the cache
- if (cacheCheckPush) {
- if (cache->inCache(prefetch->getAddr())) {
- addr++;
- delay++;
- continue;
- }
- }
-
- //Check if it is already in the miss_queue
- if (cache->inMissQueue(prefetch->getAddr())) {
- addr++;
- delay++;
- continue;
- }
-
- //Check if it is already in the pf buffer
- if (inPrefetch(prefetch->getAddr()) != pf.end()) {
- pfBufferHit++;
- addr++;
- delay++;
- continue;
- }
-
- //We just remove the head if we are full
- if (pf.size() == size)
- {
- DPRINTF(HWPrefetch, "%s:Inserting into prefetch queue, it was full removing oldest\n", cache->name());
- pfRemovedFull++;
- pf.pop_front();
- }
-
- pf.push_back(prefetch);
-
- //Make sure to request the bus, with proper delay
- cache->requestMemSideBus(BaseCache::Request_PF, prefetch->time);
-
- //Increment through the list
- addr++;
- delay++;
+ // Verify this access type is observed by prefetcher
+ if (observeAccess(pkt, miss)) {
+ if (useVirtualAddresses && pkt->req->hasVaddr()) {
+ PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss);
+ notify(pkt, pfi);
+ } else if (!useVirtualAddresses) {
+ PrefetchInfo pfi(pkt, pkt->req->getPaddr(), miss);
+ notify(pkt, pfi);
}
}
}
-std::list<PacketPtr>::iterator
-BasePrefetcher::inPrefetch(Addr address)
+void
+BasePrefetcher::regProbeListeners()
{
- //Guaranteed to only be one match, we always check before inserting
- std::list<PacketPtr>::iterator iter;
- for (iter=pf.begin(); iter != pf.end(); iter++) {
- if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) {
- return iter;
+ /**
+ * If no probes were added by the configuration scripts, connect to the
+ * parent cache using the probe "Miss". Also connect to "Hit", if the
+ * cache is configured to prefetch on accesses.
+ */
+ if (listeners.empty() && cache != nullptr) {
+ ProbeManager *pm(cache->getProbeManager());
+ listeners.push_back(new PrefetchListener(*this, pm, "Miss", false,
+ true));
+ listeners.push_back(new PrefetchListener(*this, pm, "Fill", true,
+ false));
+ if (prefetchOnAccess) {
+ listeners.push_back(new PrefetchListener(*this, pm, "Hit", false,
+ false));
}
}
- return pf.end();
}
+void
+BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
+{
+ ProbeManager *pm(obj->getProbeManager());
+ listeners.push_back(new PrefetchListener(*this, pm, name));
+}
+void
+BasePrefetcher::addTLB(BaseTLB *t)
+{
+ fatal_if(tlb != nullptr, "Only one TLB can be registered");
+ tlb = t;
+}
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