/*
+ * Copyright (c) 2013-2014 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2005 The Regents of The University of Michigan
* All rights reserved.
*
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
+ * Mitch Hayenga
*/
/**
* Miss and writeback queue declarations.
*/
-#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
-#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
-
-#include <list>
+#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
+#define __MEM_CACHE_PREFETCH_BASE_HH__
#include "base/statistics.hh"
#include "mem/packet.hh"
-#include "params/BaseCache.hh"
+#include "params/BasePrefetcher.hh"
+#include "sim/clocked_object.hh"
class BaseCache;
-class BasePrefetcher
+class BasePrefetcher : public ClockedObject
{
protected:
- /** The Prefetch Queue. */
- std::list<PacketPtr> pf;
-
// PARAMETERS
- /** The number of MSHRs in the Prefetch Queue. */
- const int size;
-
/** Pointr to the parent cache. */
BaseCache* cache;
/** The block size of the parent cache. */
- int blkSize;
+ unsigned blkSize;
- /** Do we prefetch across page boundaries. */
- bool pageStop;
+ /** log_2(block size of the parent cache). */
+ unsigned lBlkSize;
- /** Do we remove prefetches with later times than a new miss.*/
- bool serialSquash;
+ /** System we belong to */
+ System* system;
- /** Do we check if it is in the cache when inserting into buffer,
- or removing.*/
- bool cacheCheckPush;
+ /** Only consult prefetcher on cache misses? */
+ bool onMiss;
- /** Do we prefetch on only data reads, or on inst reads as well. */
- bool onlyData;
+ /** Consult prefetcher on reads? */
+ bool onRead;
- std::string _name;
+ /** Consult prefetcher on reads? */
+ bool onWrite;
- public:
-
- Stats::Scalar<> pfIdentified;
- Stats::Scalar<> pfMSHRHit;
- Stats::Scalar<> pfCacheHit;
- Stats::Scalar<> pfBufferHit;
- Stats::Scalar<> pfRemovedFull;
- Stats::Scalar<> pfRemovedMSHR;
- Stats::Scalar<> pfIssued;
- Stats::Scalar<> pfSpanPage;
- Stats::Scalar<> pfSquashed;
-
- void regStats(const std::string &name);
+ /** Consult prefetcher on data accesses? */
+ bool onData;
- public:
+ /** Consult prefetcher on instruction accesses? */
+ bool onInst;
- BasePrefetcher(const BaseCacheParams *p);
+ /** Request id for prefetches */
+ MasterID masterId;
- virtual ~BasePrefetcher() {}
+ const Addr pageBytes;
- const std::string name() const { return _name; }
+ /** Determine if this access should be observed */
+ bool observeAccess(const PacketPtr &pkt) const;
- void setCache(BaseCache *_cache);
+ /** Determine if address is in cache */
+ bool inCache(Addr addr, bool is_secure) const;
- /**
- * Notify prefetcher of cache access (may be any access or just
- * misses, depending on cache parameters.)
- * @retval Time of next prefetch availability, or 0 if none.
- */
- Tick notify(PacketPtr &pkt, Tick time);
+ /** Determine if address is in cache miss queue */
+ bool inMissQueue(Addr addr, bool is_secure) const;
- bool inCache(Addr addr);
+ /** Determine if addresses are on the same page */
+ bool samePage(Addr a, Addr b) const;
+ /** Determine the address of the block in which a lays */
+ Addr blockAddress(Addr a) const;
+ /** Determine the address of a at block granularity */
+ Addr blockIndex(Addr a) const;
+ /** Determine the address of the page in which a lays */
+ Addr pageAddress(Addr a) const;
+ /** Determine the page-offset of a */
+ Addr pageOffset(Addr a) const;
+ /** Build the address of the i-th block inside the page */
+ Addr pageIthBlockAddress(Addr page, uint32_t i) const;
- bool inMissQueue(Addr addr);
- PacketPtr getPacket();
+ Stats::Scalar pfIssued;
- bool havePending()
- {
- return !pf.empty();
- }
+ public:
- Tick nextPrefetchReadyTime()
- {
- return pf.empty() ? MaxTick : pf.front()->time;
- }
+ BasePrefetcher(const BasePrefetcherParams *p);
- virtual void calculatePrefetch(PacketPtr &pkt,
- std::list<Addr> &addresses,
- std::list<Tick> &delays) = 0;
+ virtual ~BasePrefetcher() {}
- std::list<PacketPtr>::iterator inPrefetch(Addr address);
+ void setCache(BaseCache *_cache);
/**
- * Utility function: are addresses a and b on the same VM page?
+ * Notify prefetcher of cache access (may be any access or just
+ * misses, depending on cache parameters.)
+ * @retval Time of next prefetch availability, or MaxTick if none.
*/
- bool samePage(Addr a, Addr b);
-};
+ virtual Tick notify(const PacketPtr &pkt) = 0;
+
+ virtual PacketPtr getPacket() = 0;
+ virtual Tick nextPrefetchReadyTime() const = 0;
-#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
+ virtual void regStats();
+};
+#endif //__MEM_CACHE_PREFETCH_BASE_HH__
projects / gem5.git / blobdiff