arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

[gem5.git] / src / mem / cache / queue.hh

diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index fb3e73608071de83559c4dfa2e4ed0c7dbcb7a04..36ddb96c2f6a697e502c119aa31899fe9d340bd8 100644 (file)
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -50,10 +50,15 @@
 #define __MEM_CACHE_QUEUE_HH__
 
 #include <cassert>
+#include <string>
 
+#include "base/logging.hh"
 #include "base/trace.hh"
+#include "base/types.hh"
 #include "debug/Drain.hh"
 #include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"
 #include "sim/drain.hh"
 
 /**
@@ -104,8 +109,7 @@ class Queue : public Drainable
                 return readyList.insert(i, entry);
             }
         }
-        assert(false);
-        return readyList.end();  // keep stupid compilers happy
+        panic("Failed to add to ready list.");
     }
 
     /** The number of entries that are in service. */
@@ -148,12 +152,15 @@ class Queue : public Drainable
     }
 
     /**
-     * Find the first WriteQueueEntry that matches the provided address.
+     * Find the first entry that matches the provided address.
+     *
      * @param blk_addr The block address to find.
      * @param is_secure True if the target memory space is secure.
+     * @param ignore_uncacheable Should uncacheables be ignored or not
      * @return Pointer to the matching WriteQueueEntry, null if not found.
      */
-    Entry* findMatch(Addr blk_addr, bool is_secure) const
+    Entry* findMatch(Addr blk_addr, bool is_secure,
+                     bool ignore_uncacheable = true) const
     {
         for (const auto& entry : allocatedList) {
             // we ignore any entries allocated for uncacheable
@@ -162,19 +169,19 @@ class Queue : public Drainable
             // uncacheable entries, and we do not want normal
             // cacheable accesses being added to an WriteQueueEntry
             // serving an uncacheable access
-            if (!entry->isUncacheable() && entry->blkAddr == blk_addr &&
-                entry->isSecure == is_secure) {
+            if (!(ignore_uncacheable && entry->isUncacheable()) &&
+                entry->blkAddr == blk_addr && entry->isSecure == is_secure) {
                 return entry;
             }
         }
         return nullptr;
     }
 
-    bool checkFunctional(PacketPtr pkt, Addr blk_addr)
+    bool trySatisfyFunctional(PacketPtr pkt, Addr blk_addr)
     {
         pkt->pushLabel(label);
         for (const auto& entry : allocatedList) {
-            if (entry->blkAddr == blk_addr && entry->checkFunctional(pkt)) {
+            if (entry->blkAddr == blk_addr && entry->trySatisfyFunctional(pkt)) {
                 pkt->popLabel();
                 return true;
             }
@@ -206,7 +213,7 @@ class Queue : public Drainable
     Entry* getNext() const
     {
         if (readyList.empty() || readyList.front()->readyTime > curTick()) {
-            return NULL;
+            return nullptr;
         }
         return readyList.front();
     }