/*
- * Copyright (c) 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
#define __MEM_CACHE_QUEUE_HH__
#include <cassert>
+#include <string>
#include "base/trace.hh"
+#include "base/types.hh"
#include "debug/Drain.hh"
#include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"
#include "sim/drain.hh"
/**
}
/**
- * Find the first WriteQueueEntry that matches the provided address.
+ * Find the first entry that matches the provided address.
+ *
* @param blk_addr The block address to find.
* @param is_secure True if the target memory space is secure.
+ * @param ignore_uncacheable Should uncacheables be ignored or not
* @return Pointer to the matching WriteQueueEntry, null if not found.
*/
- Entry* findMatch(Addr blk_addr, bool is_secure) const
+ Entry* findMatch(Addr blk_addr, bool is_secure,
+ bool ignore_uncacheable = true) const
{
for (const auto& entry : allocatedList) {
// we ignore any entries allocated for uncacheable
// uncacheable entries, and we do not want normal
// cacheable accesses being added to an WriteQueueEntry
// serving an uncacheable access
- if (!entry->isUncacheable() && entry->blkAddr == blk_addr &&
- entry->isSecure == is_secure) {
+ if (!(ignore_uncacheable && entry->isUncacheable()) &&
+ entry->blkAddr == blk_addr && entry->isSecure == is_secure) {
return entry;
}
}
Entry* getNext() const
{
if (readyList.empty() || readyList.front()->readyTime > curTick()) {
- return NULL;
+ return nullptr;
}
return readyList.front();
}