Cache: Fix the LRU policy for classic memory hierarchy

[gem5.git] / src / mem / cache / tags / SConscript

diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 18ed8408bbcb421e65017a27fe1332f542bce97a..a233e9684b6da842d2083d03f20879764b4fd2d9 100644 (file)
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,17 +30,17 @@
 
 Import('*')
 
-Source('base_tags.cc')
+if env['TARGET_ISA'] == 'no':
+    Return()
+
+Source('base.cc')
 Source('fa_lru.cc')
 Source('iic.cc')
 Source('lru.cc')
-Source('split.cc')
-Source('split_lifo.cc')
-Source('split_lru.cc')
+Source('cacheset.cc')
 
-SimObject('Repl.py')
-Source('repl/gen.cc')
+SimObject('iic_repl/Repl.py')
+Source('iic_repl/gen.cc')
 
-TraceFlag('IIC')
-TraceFlag('IICMore')
-TraceFlag('Split')
+DebugFlag('IIC')
+DebugFlag('IICMore')