Cache: Fix the LRU policy for classic memory hierarchy

[gem5.git] / src / mem / cache / tags / SConscript

diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 37ed5dc85aa24c8e403a044047e32a747ca13ed2..a233e9684b6da842d2083d03f20879764b4fd2d9 100644 (file)
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 Source('base.cc')
 Source('fa_lru.cc')
 Source('iic.cc')
@@ -39,5 +42,5 @@ Source('cacheset.cc')
 SimObject('iic_repl/Repl.py')
 Source('iic_repl/gen.cc')
 
-TraceFlag('IIC')
-TraceFlag('IICMore')
+DebugFlag('IIC')
+DebugFlag('IICMore')