Cache: Fix the LRU policy for classic memory hierarchy

[gem5.git] / src / mem / cache / tags / SConscript

diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 7255e0b7e1c1d7be156a8c616eb0675ef07560c8..a233e9684b6da842d2083d03f20879764b4fd2d9 100644 (file)
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,13 +30,17 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 Source('base.cc')
 Source('fa_lru.cc')
 Source('iic.cc')
 Source('lru.cc')
+Source('cacheset.cc')
 
 SimObject('iic_repl/Repl.py')
 Source('iic_repl/gen.cc')
 
-TraceFlag('IIC')
-TraceFlag('IICMore')
+DebugFlag('IIC')
+DebugFlag('IICMore')