Cache: Fix the LRU policy for classic memory hierarchy

[gem5.git] / src / mem / cache / tags / SConscript

diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index d640a9f13080931910703f7737df980fdf273b7e..a233e9684b6da842d2083d03f20879764b4fd2d9 100644 (file)
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -42,5 +42,5 @@ Source('cacheset.cc')
 SimObject('iic_repl/Repl.py')
 Source('iic_repl/gen.cc')
 
-TraceFlag('IIC')
-TraceFlag('IICMore')
+DebugFlag('IIC')
+DebugFlag('IICMore')