Cache: Fix the LRU policy for classic memory hierarchy

[gem5.git] / src / mem / cache / tags / iic.cc

diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 3501ec378e83282422bbf8d1e5da3f9c7ec0b3e0..260b891945d37bc75676cc17371176e73e2e3436 100644 (file)
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -370,8 +370,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
 */
             Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
                                            blkSize, 0, Request::wbMasterId);
-            PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback,
-                                             -1);
+            PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback);
             writeback->allocate();
             memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);