SCons: Support building without an ISA

[gem5.git] / src / mem / cache / tags / lru.cc

diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 0da2a72e926ac9a51f31cb5f8b13d5cedb7b8a9e..8a8b0d0d650c714a23eadb7d62cddb8578ec568b 100644 (file)
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -35,11 +35,11 @@
 
 #include <string>
 
-#include "mem/cache/base.hh"
 #include "base/intmath.hh"
+#include "mem/cache/base.hh"
+#include "mem/cache/tags/cacheset.hh"
 #include "mem/cache/tags/lru.hh"
 #include "sim/core.hh"
-#include "cacheset.hh"
 
 using namespace std;
 
@@ -162,6 +162,8 @@ LRU::findVictim(Addr addr, PacketList &writebacks)
         if (blk->contextSrc != -1) {
             occupancies[blk->contextSrc % cache->numCpus()]--;
             blk->contextSrc = -1;
+        } else {
+            occupancies[cache->numCpus()]--;
         }
 
         DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
@@ -188,8 +190,10 @@ LRU::insertBlock(Addr addr, BlkType *blk, int context_src)
     // deal with what we are bringing in
     if (context_src != -1) {
         occupancies[context_src % cache->numCpus()]++;
-        blk->contextSrc = context_src;
+    } else {
+        occupancies[cache->numCpus()]++;
     }
+    blk->contextSrc = context_src;
 
     unsigned set = extractSet(addr);
     sets[set].moveToHead(blk);
@@ -206,10 +210,20 @@ LRU::invalidateBlk(BlkType *blk)
         if (blk->contextSrc != -1) {
             occupancies[blk->contextSrc % cache->numCpus()]--;
             blk->contextSrc = -1;
+        } else {
+            occupancies[cache->numCpus()]--;
         }
     }
 }
 
+void
+LRU::clearLocks()
+{
+    for (int i = 0; i < numBlocks; i++){
+        blks[i].clearLoadLocks();
+    }
+}
+
 void
 LRU::cleanupRefs()
 {