/*
- * Copyright (c) 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2012-2013, 2015-2017 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
#include "mem/cache/write_queue_entry.hh"
-#include <algorithm>
#include <cassert>
#include <string>
-#include <vector>
#include "base/logging.hh"
#include "base/types.hh"
-#include "debug/Cache.hh"
-#include "mem/cache/cache.hh"
-#include "sim/core.hh"
-
-using namespace std;
+#include "mem/cache/base.hh"
+#include "mem/request.hh"
inline void
WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
"Write queue entry %#llx should never have more than one "
"cacheable target", blkAddr);
panic_if(!((target->isWrite() && _isUncacheable) ||
- (target->isEviction() && !_isUncacheable)),
- "Write queue entry %#llx should either be uncacheable write or "
- "a cacheable eviction");
+ (target->isEviction() && !_isUncacheable) ||
+ target->cmd == MemCmd::WriteClean),
+ "Write queue entry %#llx should be an uncacheable write or "
+ "a cacheable eviction or a writeclean");
targets.add(target, when_ready, _order);
}
}
bool
-WriteQueueEntry::sendPacket(Cache &cache)
+WriteQueueEntry::sendPacket(BaseCache &cache)
{
return cache.sendWriteQueuePacket(this);
}
std::string
WriteQueueEntry::print() const
{
- ostringstream str;
+ std::ostringstream str;
print(str);
return str.str();
}