mem: Fix guest corruption when caches handle uncacheable accesses

[gem5.git] / src / mem / coherent_bus.hh

diff --git a/src/mem/coherent_bus.hh b/src/mem/coherent_bus.hh
index 760ff8addb1d3b62a1f13813c2ad9adff19e92ff..61406608b5a39b8d6fcc7eab127806376f1d4b0b 100644 (file)
--- a/src/mem/coherent_bus.hh
+++ b/src/mem/coherent_bus.hh
@@ -63,12 +63,21 @@
  * The coherent bus can be used as a template for modelling QPI,
 * HyperTransport, ACE and coherent OCP buses, and is typically used
  * for the L1-to-L2 buses and as the main system interconnect.
+ * @sa  \ref gem5MemorySystem "gem5 Memory System"
  */
 class CoherentBus : public BaseBus
 {
 
   protected:
 
+    /**
+     * Declare the three layers of this bus, one for requests, one
+     * for responses, and one for snoop responses
+     */
+    Layer<SlavePort> reqLayer;
+    Layer<MasterPort> respLayer;
+    Layer<SlavePort> snoopRespLayer;
+
     /**
      * Declaration of the coherent bus slave port type, one will be
      * instantiated for each of the master ports connecting to the
@@ -124,14 +133,14 @@ class CoherentBus : public BaseBus
         /**
          * Return the union of all adress ranges seen by this bus.
          */
-        virtual AddrRangeList getAddrRanges()
+        virtual AddrRangeList getAddrRanges() const
         { return bus.getAddrRanges(); }
 
         /**
          * Get the maximum block size as seen by the bus.
          */
         virtual unsigned deviceBlockSize() const
-        { return bus.findBlockSize(); }
+        { return bus.deviceBlockSize(); }
 
     };
 
@@ -202,7 +211,7 @@ class CoherentBus : public BaseBus
         // take the max of it. This might need to be changed a bit if we ever
         // support multiple block sizes.
         virtual unsigned deviceBlockSize() const
-        { return bus.findBlockSize(); }
+        { return bus.deviceBlockSize(); }
 
     };
 
@@ -217,19 +226,23 @@ class CoherentBus : public BaseBus
 
     /** Function called by the port when the bus is recieving a Timing
       request packet.*/
-    bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
+    virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
 
     /** Function called by the port when the bus is recieving a Timing
       response packet.*/
-    bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
+    virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
 
     /** Function called by the port when the bus is recieving a timing
         snoop request.*/
-    void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id);
+    virtual void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id);
 
     /** Function called by the port when the bus is recieving a timing
         snoop response.*/
-    bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id);
+    virtual bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id);
+
+    /** Timing function called by port when it is once again able to process
+     * requests. */
+    void recvRetry();
 
     /**
      * Forward a timing packet to our snoopers, potentially excluding
@@ -285,6 +298,8 @@ class CoherentBus : public BaseBus
     virtual void init();
 
     CoherentBus(const CoherentBusParams *p);
+
+    unsigned int drain(DrainManager *dm);
 };
 
 #endif //__MEM_COHERENT_BUS_HH__