mem: Fix guest corruption when caches handle uncacheable accesses

[gem5.git] / src / mem / coherent_bus.hh

diff --git a/src/mem/coherent_bus.hh b/src/mem/coherent_bus.hh
index a28b388d5c024e529d38229b682752558738db21..61406608b5a39b8d6fcc7eab127806376f1d4b0b 100644 (file)
--- a/src/mem/coherent_bus.hh
+++ b/src/mem/coherent_bus.hh
@@ -63,6 +63,7 @@
  * The coherent bus can be used as a template for modelling QPI,
 * HyperTransport, ACE and coherent OCP buses, and is typically used
  * for the L1-to-L2 buses and as the main system interconnect.
+ * @sa  \ref gem5MemorySystem "gem5 Memory System"
  */
 class CoherentBus : public BaseBus
 {
@@ -139,7 +140,7 @@ class CoherentBus : public BaseBus
          * Get the maximum block size as seen by the bus.
          */
         virtual unsigned deviceBlockSize() const
-        { return bus.findBlockSize(); }
+        { return bus.deviceBlockSize(); }
 
     };
 
@@ -210,7 +211,7 @@ class CoherentBus : public BaseBus
         // take the max of it. This might need to be changed a bit if we ever
         // support multiple block sizes.
         virtual unsigned deviceBlockSize() const
-        { return bus.findBlockSize(); }
+        { return bus.deviceBlockSize(); }
 
     };
 
@@ -298,7 +299,7 @@ class CoherentBus : public BaseBus
 
     CoherentBus(const CoherentBusParams *p);
 
-    unsigned int drain(Event *de);
+    unsigned int drain(DrainManager *dm);
 };
 
 #endif //__MEM_COHERENT_BUS_HH__