* The coherent bus can be used as a template for modelling QPI,
* HyperTransport, ACE and coherent OCP buses, and is typically used
* for the L1-to-L2 buses and as the main system interconnect.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
*/
class CoherentBus : public BaseBus
{
protected:
/**
- * Declare the single layer of this bus.
+ * Declare the three layers of this bus, one for requests, one
+ * for responses, and one for snoop responses
*/
- Layer layer;
+ Layer<SlavePort> reqLayer;
+ Layer<MasterPort> respLayer;
+ Layer<SlavePort> snoopRespLayer;
/**
* Declaration of the coherent bus slave port type, one will be
* Get the maximum block size as seen by the bus.
*/
virtual unsigned deviceBlockSize() const
- { return bus.findBlockSize(); }
+ { return bus.deviceBlockSize(); }
};
// take the max of it. This might need to be changed a bit if we ever
// support multiple block sizes.
virtual unsigned deviceBlockSize() const
- { return bus.findBlockSize(); }
+ { return bus.deviceBlockSize(); }
};
CoherentBus(const CoherentBusParams *p);
- unsigned int drain(Event *de);
+ unsigned int drain(DrainManager *dm);
};
#endif //__MEM_COHERENT_BUS_HH__