mem: Support for specifying the destination of a WriteClean

[gem5.git] / src / mem / coherent_xbar.hh

diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh
index 214a29071a660a40f95ed20853de3d39bec990b7..0c2907fa0f4e26d541ae2b438cf9680f82b6cc54 100644 (file)
--- a/src/mem/coherent_xbar.hh
+++ b/src/mem/coherent_xbar.hh
@@ -398,6 +398,29 @@ class CoherentXBar : public BaseXBar
      */
     bool sinkPacket(const PacketPtr pkt) const;
 
+    /**
+     * Determine if the crossbar should forward the packet, as opposed to
+     * responding to it.
+     */
+    bool forwardPacket(const PacketPtr pkt);
+
+    /**
+     * Determine if the packet's destination is the memory below
+     *
+     * The memory below is the destination for a cache mainteance
+     * operation to the Point of Coherence/Unification if this is the
+     * Point of Coherence/Unification.
+     *
+     * @param pkt The processed packet
+     *
+     * @return Whether the memory below is the destination for the packet
+     */
+    bool isDestination(const PacketPtr pkt) const
+    {
+        return (pkt->req->isToPOC() && pointOfCoherency) ||
+            (pkt->req->isToPOU() && pointOfUnification);
+    }
+
     Stats::Scalar snoops;
     Stats::Scalar snoopTraffic;
     Stats::Distribution snoopFanout;