#include "base/statistics.hh"
#include "mem/physical.hh"
+#include "params/DRAMMemory.hh"
class DRAMMemory : public PhysicalMemory
{
Tick time_last_access;
- Stats::Vector<> accesses;
- Stats::Vector<> bytesRequested;
- Stats::Vector<> bytesSent;
- Stats::Vector<> compressedAccesses;
-
- Stats::Vector<> cycles_nCKE;
- Stats::Vector<> cycles_all_precharge_CKE;
- Stats::Vector<> cycles_all_precharge_nCKE;
- Stats::Vector<> cycles_bank_active_nCKE;
- Stats::Vector<> cycles_avg_ACT;
- Stats::Vector<> cycles_read_out;
- Stats::Vector<> cycles_write_in;
- Stats::Vector<> cycles_between_misses;
- Stats::Vector<> other_bank_read_access_miss;
- Stats::Vector<> other_bank_write_access_miss;
- Stats::Scalar<> total_latency;
- Stats::Scalar<> total_icache_req;
- Stats::Scalar<> total_arb_latency;
+ Stats::Vector accesses;
+ Stats::Vector bytesRequested;
+ Stats::Vector bytesSent;
+ Stats::Vector compressedAccesses;
+
+ Stats::Vector cycles_nCKE;
+ Stats::Vector cycles_all_precharge_CKE;
+ Stats::Vector cycles_all_precharge_nCKE;
+ Stats::Vector cycles_bank_active_nCKE;
+ Stats::Vector cycles_avg_ACT;
+ Stats::Vector cycles_read_out;
+ Stats::Vector cycles_write_in;
+ Stats::Vector cycles_between_misses;
+ Stats::Vector other_bank_read_access_miss;
+ Stats::Vector other_bank_write_access_miss;
+ Stats::Scalar total_latency;
+ Stats::Scalar total_icache_req;
+ Stats::Scalar total_arb_latency;
Stats::Formula avg_latency;
Stats::Formula avg_arb_latency;
- Stats::Vector2d<> bank_access_profile;
+ Stats::Vector2d bank_access_profile;
protected:
int prechargeBanksAround(int bank);
public:
- struct Params : public PhysicalMemory::Params
+ typedef DRAMMemoryParams Params;
+ DRAMMemory(const Params *p);
+
+ const Params *
+ params() const
{
- /* additional params for dram protocol*/
- int cpu_ratio;
- int bus_width;
-
- std::string mem_type; /* DRDRAM, SDRAM */
- std::string mem_actpolicy; /* closed, open */
- std::string memctrladdr_type; /* interleaved, anythingelse */
-
- int act_lat;
- int cas_lat;
- int war_lat;
- int pre_lat;
- int dpl_lat;
- int trc_lat;
- int num_banks;
- int num_cpus;
-
- };
+ return dynamic_cast<const Params *>(_params);
+ }
+
virtual void regStats();
- DRAMMemory(Params *p);
};
#endif// __MEM_DRAM_HH__