}
DRAMCtrl::DRAMPacket*
-DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
- bool isRead)
+DRAMCtrl::decodeAddr(const PacketPtr pkt, Addr dramPktAddr, unsigned size,
+ bool isRead) const
{
// decode the address based on the address mapping scheme, with
// Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
qosSchedule( { &readQueue, &writeQueue }, burstSize, pkt);
// check local buffers and do not accept if full
- if (pkt->isRead()) {
- assert(size != 0);
- if (readQueueFull(dram_pkt_count)) {
- DPRINTF(DRAM, "Read queue full, not accepting\n");
- // remember that we have to retry this port
- retryRdReq = true;
- numRdRetry++;
- return false;
- } else {
- addToReadQueue(pkt, dram_pkt_count);
- readReqs++;
- bytesReadSys += size;
- }
- } else {
- assert(pkt->isWrite());
+ if (pkt->isWrite()) {
assert(size != 0);
if (writeQueueFull(dram_pkt_count)) {
DPRINTF(DRAM, "Write queue full, not accepting\n");
writeReqs++;
bytesWrittenSys += size;
}
+ } else {
+ assert(pkt->isRead());
+ assert(size != 0);
+ if (readQueueFull(dram_pkt_count)) {
+ DPRINTF(DRAM, "Read queue full, not accepting\n");
+ // remember that we have to retry this port
+ retryRdReq = true;
+ numRdRetry++;
+ return false;
+ } else {
+ addToReadQueue(pkt, dram_pkt_count);
+ readReqs++;
+ bytesReadSys += size;
+ }
}
return true;