p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
retryReq(false), retryResp(false), startTick(0),
nbrOutstandingReads(0), nbrOutstandingWrites(0),
- sendResponseEvent(this), tickEvent(this)
+ sendResponseEvent([this]{ sendResponse(); }, name()),
+ tickEvent([this]{ tick(); }, name())
{
DPRINTF(DRAMSim2,
"Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
// potentially update the packets in our response queue as well
for (auto i = responseQueue.begin(); i != responseQueue.end(); ++i)
- pkt->checkFunctional(*i);
+ pkt->trySatisfyFunctional(*i);
pkt->popLabel();
}
signalDrainDone();
}
-BaseSlavePort&
-DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+DRAMSim2::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getSlavePort(if_name, idx);
+ return AbstractMemory::getPort(if_name, idx);
} else {
return port;
}