* Authors: Andreas Hansson
*/
+#include "mem/dramsim2.hh"
+
#include "DRAMSim2/Callback.h"
#include "base/callback.hh"
#include "base/trace.hh"
#include "debug/DRAMSim2.hh"
#include "debug/Drain.hh"
-#include "mem/dramsim2.hh"
#include "sim/system.hh"
DRAMSim2::DRAMSim2(const Params* p) :
p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
retryReq(false), retryResp(false), startTick(0),
nbrOutstandingReads(0), nbrOutstandingWrites(0),
- sendResponseEvent(this), tickEvent(this)
+ sendResponseEvent([this]{ sendResponse(); }, name()),
+ tickEvent([this]{ tick(); }, name())
{
DPRINTF(DRAMSim2,
"Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
access(pkt);
// 50 ns is just an arbitrary value at this point
- return pkt->memInhibitAsserted() ? 0 : 50000;
+ return pkt->cacheResponding() ? 0 : 50000;
}
void
// potentially update the packets in our response queue as well
for (auto i = responseQueue.begin(); i != responseQueue.end(); ++i)
- pkt->checkFunctional(*i);
+ pkt->trySatisfyFunctional(*i);
pkt->popLabel();
}
bool
DRAMSim2::recvTimingReq(PacketPtr pkt)
{
- // we should never see a new request while in retry
- assert(!retryReq);
-
- // @todo temporary hack to deal with memory corruption issues until
- // 4-phase transactions are complete
- for (int x = 0; x < pendingDelete.size(); x++)
- delete pendingDelete[x];
- pendingDelete.clear();
-
- if (pkt->memInhibitAsserted()) {
- // snooper will supply based on copy of packet
- // still target's responsibility to delete packet
- pendingDelete.push_back(pkt);
+ // if a cache is responding, sink the packet without further action
+ if (pkt->cacheResponding()) {
+ pendingDelete.reset(pkt);
return true;
}
+ // we should not get a new request after committing to retry the
+ // current one, but unfortunately the CPU violates this rule, so
+ // simply ignore it for now
+ if (retryReq)
+ return false;
+
// if we cannot accept we need to send a retry once progress can
// be made
bool can_accept = nbrOutstanding() < wrapper.queueSize();
if (!retryResp && !sendResponseEvent.scheduled())
schedule(sendResponseEvent, time);
} else {
- // @todo the packet is going to be deleted, and the DRAMPacket
- // is still having a pointer to it
- pendingDelete.push_back(pkt);
+ // queue the packet for deletion
+ pendingDelete.reset(pkt);
}
}
signalDrainDone();
}
-BaseSlavePort&
-DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+DRAMSim2::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getSlavePort(if_name, idx);
+ return AbstractMemory::getPort(if_name, idx);
} else {
return port;
}