mem-cache: Add match functions to QueueEntry

[gem5.git] / src / mem / dramsim2.hh

diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 5cde19cd87af59e2810f75e4239ba22413faaba8..2fd140bb43cbfed4e5529da174bc009327a1eee5 100644 (file)
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -148,7 +148,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule sending of responses
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+    EventFunctionWrapper sendResponseEvent;
 
     /**
      * Progress the controller one clock cycle.
@@ -158,7 +158,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule clock ticks
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+    EventFunctionWrapper tickEvent;
 
     /**
      * Upstream caches need this packet until true is returned, so
@@ -191,8 +191,8 @@ class DRAMSim2 : public AbstractMemory
 
     DrainState drain() override;
 
-    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
-                                        PortID idx = InvalidPortID) override;
+    Port &getPort(const std::string &if_name,
+                  PortID idx=InvalidPortID) override;
 
     void init() override;
     void startup() override;