#define __MEM_DRAMSIM2_HH__
#include <queue>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/abstract_mem.hh"
#include "mem/dramsim2_wrapper.hh"
#include "mem/qport.hh"
bool recvTimingReq(PacketPtr pkt);
- void recvRetry();
+ void recvRespRetry();
AddrRangeList getAddrRanges() const;
*/
bool retryResp;
+ /**
+ * Keep track of when the wrapper is started.
+ */
+ Tick startTick;
+
/**
* Keep track of what packets are outstanding per
* address, and do so separately for reads and writes. This is
* done so that we can return the right packet on completion from
* DRAMSim.
*/
- m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads;
- m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites;
+ std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
+ std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
/**
* Count the number of outstanding transactions so that we can
*/
std::deque<PacketPtr> responseQueue;
- /**
- * If we need to drain, keep the drain manager around until we're
- * done here.
- */
- DrainManager *drainManager;
-
unsigned int nbrOutstanding() const;
/**
/**
* Event to schedule sending of responses
*/
- EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+ EventFunctionWrapper sendResponseEvent;
/**
* Progress the controller one clock cycle.
/**
* Event to schedule clock ticks
*/
- EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+ EventFunctionWrapper tickEvent;
- /** @todo this is a temporary workaround until the 4-phase code is
- * committed. upstream caches needs this packet until true is returned, so
- * hold onto it for deletion until a subsequent call
+ /**
+ * Upstream caches need this packet until true is returned, so
+ * hold it for deletion until a subsequent call
*/
- std::vector<PacketPtr> pendingDelete;
+ std::unique_ptr<Packet> pendingDelete;
public:
*/
void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
- unsigned int drain(DrainManager* dm);
+ DrainState drain() override;
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
- virtual void init();
- virtual void startup();
+ void init() override;
+ void startup() override;
protected:
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr pkt);
- void recvRetry();
+ void recvRespRetry();
};