mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / dramsim2.hh

diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 5cde19cd87af59e2810f75e4239ba22413faaba8..6444f75d646a7b30d596f9e1ec5808cf229495f3 100644 (file)
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -148,7 +148,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule sending of responses
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+    EventFunctionWrapper sendResponseEvent;
 
     /**
      * Progress the controller one clock cycle.
@@ -158,7 +158,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule clock ticks
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+    EventFunctionWrapper tickEvent;
 
     /**
      * Upstream caches need this packet until true is returned, so