mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / dramsim2.hh

diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 7153f3f848e240b1169ef21dd5c9696c66ca9df8..6444f75d646a7b30d596f9e1ec5808cf229495f3 100644 (file)
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -45,8 +45,8 @@
 #define __MEM_DRAMSIM2_HH__
 
 #include <queue>
+#include <unordered_map>
 
-#include "base/hashmap.hh"
 #include "mem/abstract_mem.hh"
 #include "mem/dramsim2_wrapper.hh"
 #include "mem/qport.hh"
@@ -80,7 +80,7 @@ class DRAMSim2 : public AbstractMemory
 
         bool recvTimingReq(PacketPtr pkt);
 
-        void recvRetry();
+        void recvRespRetry();
 
         AddrRangeList getAddrRanges() const;
 
@@ -114,8 +114,8 @@ class DRAMSim2 : public AbstractMemory
      * done so that we can return the right packet on completion from
      * DRAMSim.
      */
-    m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads;
-    m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites;
+    std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
+    std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
 
     /**
      * Count the number of outstanding transactions so that we can
@@ -132,12 +132,6 @@ class DRAMSim2 : public AbstractMemory
      */
     std::deque<PacketPtr> responseQueue;
 
-    /**
-     * If we need to drain, keep the drain manager around until we're
-     * done here.
-     */
-    DrainManager *drainManager;
-
     unsigned int nbrOutstanding() const;
 
     /**
@@ -154,7 +148,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule sending of responses
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+    EventFunctionWrapper sendResponseEvent;
 
     /**
      * Progress the controller one clock cycle.
@@ -164,13 +158,13 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule clock ticks
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+    EventFunctionWrapper tickEvent;
 
-    /** @todo this is a temporary workaround until the 4-phase code is
-     * committed. upstream caches needs this packet until true is returned, so
-     * hold onto it for deletion until a subsequent call
+    /**
+     * Upstream caches need this packet until true is returned, so
+     * hold it for deletion until a subsequent call
      */
-    std::vector<PacketPtr> pendingDelete;
+    std::unique_ptr<Packet> pendingDelete;
 
   public:
 
@@ -195,20 +189,20 @@ class DRAMSim2 : public AbstractMemory
      */
     void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
 
-    unsigned int drain(DrainManager* dm);
+    DrainState drain() override;
 
     virtual BaseSlavePort& getSlavePort(const std::string& if_name,
-                                        PortID idx = InvalidPortID);
+                                        PortID idx = InvalidPortID) override;
 
-    virtual void init();
-    virtual void startup();
+    void init() override;
+    void startup() override;
 
   protected:
 
     Tick recvAtomic(PacketPtr pkt);
     void recvFunctional(PacketPtr pkt);
     bool recvTimingReq(PacketPtr pkt);
-    void recvRetry();
+    void recvRespRetry();
 
 };