mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / dramsim2.hh

diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 77486de889ca3c958ee2fd586b863c5f33992810..6444f75d646a7b30d596f9e1ec5808cf229495f3 100644 (file)
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -148,7 +148,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule sending of responses
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+    EventFunctionWrapper sendResponseEvent;
 
     /**
      * Progress the controller one clock cycle.
@@ -158,13 +158,13 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule clock ticks
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+    EventFunctionWrapper tickEvent;
 
-    /** @todo this is a temporary workaround until the 4-phase code is
-     * committed. upstream caches needs this packet until true is returned, so
-     * hold onto it for deletion until a subsequent call
+    /**
+     * Upstream caches need this packet until true is returned, so
+     * hold it for deletion until a subsequent call
      */
-    std::vector<PacketPtr> pendingDelete;
+    std::unique_ptr<Packet> pendingDelete;
 
   public:
 
@@ -192,10 +192,10 @@ class DRAMSim2 : public AbstractMemory
     DrainState drain() override;
 
     virtual BaseSlavePort& getSlavePort(const std::string& if_name,
-                                        PortID idx = InvalidPortID);
+                                        PortID idx = InvalidPortID) override;
 
-    virtual void init();
-    virtual void startup();
+    void init() override;
+    void startup() override;
 
   protected: