cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / external_master.cc

diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc
index e0e8c1e87bfd0508d1436dde9cc6f039d6ca9ab1..d530d9ad02b12774f04e2dccc7954861d7b265c3 100644 (file)
--- a/src/mem/external_master.cc
+++ b/src/mem/external_master.cc
@@ -52,17 +52,16 @@ std::map<std::string, ExternalMaster::Handler *>
     ExternalMaster::portHandlers;
 
 ExternalMaster::ExternalMaster(ExternalMasterParams *params) :
-    MemObject(params),
+    SimObject(params),
     externalPort(NULL),
     portName(params->name + ".port"),
     portType(params->port_type),
     portData(params->port_data),
-    masterId(params->system->getMasterId(params->name))
+    masterId(params->system->getMasterId(this))
 {}
 
-BaseMasterPort &
-ExternalMaster::getMasterPort(const std::string &if_name,
-    PortID idx)
+Port &
+ExternalMaster::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name == "port") {
         DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n",
@@ -84,7 +83,7 @@ ExternalMaster::getMasterPort(const std::string &if_name,
         }
         return *externalPort;
     } else {
-        return MemObject::getMasterPort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }