mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / fs_translating_port_proxy.cc

diff --git a/src/mem/fs_translating_port_proxy.cc b/src/mem/fs_translating_port_proxy.cc
index 9f1f7d019d5cad5ffa072d2afbb859ac5ba97231..15ad8238c11bc5931db0cc1726165ae7e750af99 100644 (file)
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011,2013 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -46,20 +46,23 @@
  * Port object definitions.
  */
 
+#include "mem/fs_translating_port_proxy.hh"
+
+#include "arch/vtophys.hh"
 #include "base/chunk_generator.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
-
-using namespace TheISA;
+#include "sim/system.hh"
 
 FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc)
-    : PortProxy(tc->getCpuPtr()->getDataPort()), _tc(tc)
+    : PortProxy(tc->getCpuPtr()->getDataPort(),
+                tc->getSystemPtr()->cacheLineSize()), _tc(tc)
 {
 }
 
-FSTranslatingPortProxy::FSTranslatingPortProxy(MasterPort &port)
-    : PortProxy(port), _tc(NULL)
+FSTranslatingPortProxy::FSTranslatingPortProxy(MasterPort &port,
+                                               unsigned int cacheLineSize)
+    : PortProxy(port, cacheLineSize), _tc(NULL)
 {
 }
 
@@ -79,13 +82,13 @@ FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) const
         else
             paddr = TheISA::vtophys(gen.addr());
 
-        PortProxy::readBlob(paddr, p, gen.size());
+        PortProxy::readBlobPhys(paddr, 0, p, gen.size());
         p += gen.size();
     }
 }
 
 void
-FSTranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size) const
+FSTranslatingPortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
 {
     Addr paddr;
     for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -96,7 +99,7 @@ FSTranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size) const
         else
             paddr = TheISA::vtophys(gen.addr());
 
-        PortProxy::writeBlob(paddr, p, gen.size());
+        PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
         p += gen.size();
     }
 }
@@ -113,7 +116,7 @@ FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) const
         else
             paddr = TheISA::vtophys(gen.addr());
 
-        PortProxy::memsetBlob(paddr, v, gen.size());
+        PortProxy::memsetBlobPhys(paddr, 0, v, gen.size());
     }
 }
 
@@ -125,7 +128,7 @@ CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
 }
 
 void
-CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
+CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t cplen)
 {
     uint8_t *src = (uint8_t *)source;
     tc->getVirtProxy().writeBlob(dest, src, cplen);
@@ -150,7 +153,7 @@ CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
 }
 
 void
-CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
+CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr)
 {
     FSTranslatingPortProxy &vp = tc->getVirtProxy();
     for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();