ruby: handle llsc accesses through CacheEntry, not CacheMemory

[gem5.git] / src / mem / fs_translating_port_proxy.hh

diff --git a/src/mem/fs_translating_port_proxy.hh b/src/mem/fs_translating_port_proxy.hh
index c022f3d09db01ea2f3e6ac827b907c8a0a4f0a37..8120f96ea1caf3d5932196e7d35b2dc54ba37100 100644 (file)
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -59,9 +59,10 @@
 #ifndef __MEM_FS_PORT_PROXY_HH__
 #define __MEM_FS_PORT_PROXY_HH__
 
-#include "arch/vtophys.hh"
 #include "mem/port_proxy.hh"
 
+class ThreadContext;
+
 /**
  * A TranslatingPortProxy in FS mode translates a virtual address to a
  * physical address and then calls the read/write functions of the
@@ -78,7 +79,7 @@ class FSTranslatingPortProxy : public PortProxy
 
     FSTranslatingPortProxy(ThreadContext* tc);
 
-    FSTranslatingPortProxy(MasterPort &port);
+    FSTranslatingPortProxy(MasterPort &port, unsigned int cacheLineSize);
 
     virtual ~FSTranslatingPortProxy();
 
@@ -88,7 +89,7 @@ class FSTranslatingPortProxy : public PortProxy
 
     /** Version of writeBlob that translates virt->phys and deals
       * with page boundries. */
-    virtual void writeBlob(Addr addr, uint8_t *p, int size) const;
+    virtual void writeBlob(Addr addr, const uint8_t *p, int size) const;
 
     /**
      * Fill size bytes starting at addr with byte value val.
@@ -97,8 +98,8 @@ class FSTranslatingPortProxy : public PortProxy
 };
 
 void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
-void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen);
+void CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t cplen);
 void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
+void CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr);
 
 #endif //__MEM_FS_PORT_PROXY_HH__