Ruby NetDest: add assert for bad element in netdest

[gem5.git] / src / mem / mem_object.cc

diff --git a/src/mem/mem_object.cc b/src/mem/mem_object.cc
index d4d3fd283eb227cd8d2470d194794d80809b59a5..ce8badbe7bea72a85c49a371ec34acde57608817 100644 (file)
--- a/src/mem/mem_object.cc
+++ b/src/mem/mem_object.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -26,14 +38,24 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Steve Reinhardt
+ *          Andreas Hansson
  */
 
 #include "mem/mem_object.hh"
-#include "sim/param.hh"
 
-MemObject::MemObject(const std::string &name)
-    : SimObject(name)
+MemObject::MemObject(const Params *params)
+    : SimObject(params)
 {
 }
 
-DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)
+MasterPort&
+MemObject::getMasterPort(const std::string& if_name, int idx)
+{
+    fatal("%s does not have any master port named %s\n", name(), if_name);
+}
+
+SlavePort&
+MemObject::getSlavePort(const std::string& if_name, int idx)
+{
+    fatal("%s does not have any slave port named %s\n", name(), if_name);
+}