mem: Include WriteLineReq in cache demand stats

[gem5.git] / src / mem / mport.hh

diff --git a/src/mem/mport.hh b/src/mem/mport.hh
index 9bc437c52393009b9d925dc0491ac18b0ff1d83e..72d0b096294b5f0b1b98bc5d66a757a2789215b6 100644 (file)
--- a/src/mem/mport.hh
+++ b/src/mem/mport.hh
@@ -49,7 +49,7 @@
 /*
  * This file defines a port class which is used for sending and receiving
  * messages. These messages are atomic units which don't interact and
- * should be smaller than a cache block. This class is based on 
+ * should be smaller than a cache block. This class is based on
  * the underpinnings of SimpleTimingPort, but it tweaks some of the external
  * functions.
  */