ruby: handle llsc accesses through CacheEntry, not CacheMemory

[gem5.git] / src / mem / multi_level_page_table.hh

diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh
index 8d9febac8993f1e0a3629b8fc191bbfb7d346cb3..f622bbbed07a70d722b8210128613c9630a72e51 100644 (file)
--- a/src/mem/multi_level_page_table.hh
+++ b/src/mem/multi_level_page_table.hh
@@ -147,12 +147,13 @@ public:
 
     void initState(ThreadContext* tc);
 
-    void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
+    void map(Addr vaddr, Addr paddr, int64_t size,
+             uint64_t flags = 0);
     void remap(Addr vaddr, int64_t size, Addr new_vaddr);
     void unmap(Addr vaddr, int64_t size);
     bool isUnmapped(Addr vaddr, int64_t size);
     bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
-    void serialize(std::ostream &os);
-    void unserialize(Checkpoint *cp, const std::string &section);
+    void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+    void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
 };
 #endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__