ruby: handle llsc accesses through CacheEntry, not CacheMemory

[gem5.git] / src / mem / multi_level_page_table.hh

diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh
index 9ae86924d6e7a88751889e2ab938ea1d06a96574..f622bbbed07a70d722b8210128613c9630a72e51 100644 (file)
--- a/src/mem/multi_level_page_table.hh
+++ b/src/mem/multi_level_page_table.hh
@@ -141,17 +141,19 @@ class MultiLevelPageTable : public PageTableBase
     bool walk(Addr vaddr, bool allocate, Addr &PTE_addr);
 
 public:
-    MultiLevelPageTable(const std::string &__name, uint64_t _pid, System *_sys);
+    MultiLevelPageTable(const std::string &__name, uint64_t _pid,
+                        System *_sys);
     ~MultiLevelPageTable();
 
     void initState(ThreadContext* tc);
 
-    void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
+    void map(Addr vaddr, Addr paddr, int64_t size,
+             uint64_t flags = 0);
     void remap(Addr vaddr, int64_t size, Addr new_vaddr);
     void unmap(Addr vaddr, int64_t size);
     bool isUnmapped(Addr vaddr, int64_t size);
     bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
-    void serialize(std::ostream &os);
-    void unserialize(Checkpoint *cp, const std::string &section);
+    void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+    void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
 };
 #endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__