/*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
protected:
+ /**
+ * Declare the two layers of this bus, one for requests and one
+ * for responses.
+ */
+ Layer<SlavePort> reqLayer;
+ Layer<MasterPort> respLayer;
+
/**
* Declaration of the non-coherent bus slave port type, one will
* be instantiated for each of the master ports connecting to the
* Get the maximum block size as seen by the bus.
*/
virtual unsigned deviceBlockSize() const
- { return bus.findBlockSize(); }
+ { return bus.deviceBlockSize(); }
};
* Get the maximum block size as seen by the bus.
*/
virtual unsigned deviceBlockSize() const
- { return bus.findBlockSize(); }
+ { return bus.deviceBlockSize(); }
};
response packet.*/
virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
+ /** Timing function called by port when it is once again able to process
+ * requests. */
+ void recvRetry();
+
/** Function called by the port when the bus is recieving a Atomic
transaction.*/
Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
NoncoherentBus(const NoncoherentBusParams *p);
+ unsigned int drain(DrainManager *dm);
+
};
#endif //__MEM_NONCOHERENT_BUS_HH__