mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / packet.cc

diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index ffda3d5af65976f184845851e4bd1dc968d0a7ed..7a81cdbb71159969313eaed1d82692c73e5f9480 100644 (file)
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2017 ARM Limited
+ * Copyright (c) 2011-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
 #include "base/cprintf.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
+#include "mem/packet_access.hh"
 
 using namespace std;
 
@@ -364,6 +365,45 @@ Packet::popSenderState()
     return sender_state;
 }
 
+uint64_t
+Packet::getUintX(ByteOrder endian) const
+{
+    switch(getSize()) {
+      case 1:
+        return (uint64_t)get<uint8_t>(endian);
+      case 2:
+        return (uint64_t)get<uint16_t>(endian);
+      case 4:
+        return (uint64_t)get<uint32_t>(endian);
+      case 8:
+        return (uint64_t)get<uint64_t>(endian);
+      default:
+        panic("%i isn't a supported word size.\n", getSize());
+    }
+}
+
+void
+Packet::setUintX(uint64_t w, ByteOrder endian)
+{
+    switch(getSize()) {
+      case 1:
+        set<uint8_t>((uint8_t)w, endian);
+        break;
+      case 2:
+        set<uint16_t>((uint16_t)w, endian);
+        break;
+      case 4:
+        set<uint32_t>((uint32_t)w, endian);
+        break;
+      case 8:
+        set<uint64_t>((uint64_t)w, endian);
+        break;
+      default:
+        panic("%i isn't a supported word size.\n", getSize());
+    }
+
+}
+
 void
 Packet::print(ostream &o, const int verbosity, const string &prefix) const
 {