/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
/**
* @file
- * Definitions of page table.
+ * Definitions of functional page table.
*/
-#include <string>
-#include <map>
#include <fstream>
+#include <map>
+#include <memory>
+#include <string>
-#include "arch/faults.hh"
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/MMU.hh"
#include "mem/page_table.hh"
-#include "sim/process.hh"
+#include "sim/faults.hh"
#include "sim/sim_object.hh"
-#include "sim/system.hh"
using namespace std;
using namespace TheISA;
-PageTable::PageTable(Process *_process, Addr _pageSize)
- : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
- process(_process)
+FuncPageTable::FuncPageTable(const std::string &__name,
+ uint64_t _pid, Addr _pageSize)
+ : PageTableBase(__name, _pid, _pageSize)
{
- assert(isPowerOf2(pageSize));
- pTableCache[0].vaddr = 0;
- pTableCache[1].vaddr = 0;
- pTableCache[2].vaddr = 0;
}
-PageTable::~PageTable()
+FuncPageTable::~FuncPageTable()
{
}
void
-PageTable::allocate(Addr vaddr, int64_t size)
+FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags)
{
+ bool clobber = flags & Clobber;
// starting address must be page aligned
assert(pageOffset(vaddr) == 0);
DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
- for (; size > 0; size -= pageSize, vaddr += pageSize) {
- PTableItr iter = pTable.find(vaddr);
-
- if (iter != pTable.end()) {
+ for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
+ if (!clobber && (pTable.find(vaddr) != pTable.end())) {
// already mapped
- fatal("PageTable::allocate: address 0x%x already mapped",
- vaddr);
+ fatal("FuncPageTable::allocate: addr 0x%x already mapped", vaddr);
}
- pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
- process->system->new_page());
+ pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr,
+ flags & Uncacheable,
+ flags & ReadOnly);
+ eraseCacheEntry(vaddr);
updateCache(vaddr, pTable[vaddr]);
}
}
void
-PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
+FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
{
assert(pageOffset(vaddr) == 0);
assert(pageOffset(new_vaddr) == 0);
DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
new_vaddr, size);
- for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
- PTableItr iter = pTable.find(vaddr);
-
- assert(iter != pTable.end());
+ for (; size > 0;
+ size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
+ {
+ assert(pTable.find(vaddr) != pTable.end());
pTable[new_vaddr] = pTable[vaddr];
pTable.erase(vaddr);
+ eraseCacheEntry(vaddr);
pTable[new_vaddr].updateVaddr(new_vaddr);
updateCache(new_vaddr, pTable[new_vaddr]);
}
}
void
-PageTable::deallocate(Addr vaddr, int64_t size)
+FuncPageTable::unmap(Addr vaddr, int64_t size)
{
assert(pageOffset(vaddr) == 0);
- DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
+ DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
- PTableItr iter = pTable.find(vaddr);
+ assert(pTable.find(vaddr) != pTable.end());
+ pTable.erase(vaddr);
+ eraseCacheEntry(vaddr);
+ }
- assert(iter != pTable.end());
+}
- pTable.erase(vaddr);
+bool
+FuncPageTable::isUnmapped(Addr vaddr, int64_t size)
+{
+ // starting address must be page aligned
+ assert(pageOffset(vaddr) == 0);
+
+ for (; size > 0; size -= pageSize, vaddr += pageSize) {
+ if (pTable.find(vaddr) != pTable.end()) {
+ return false;
+ }
}
+ return true;
}
bool
-PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
+FuncPageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
{
Addr page_addr = pageAlign(vaddr);
- if (pTableCache[0].vaddr == page_addr) {
+ if (pTableCache[0].valid && pTableCache[0].vaddr == page_addr) {
entry = pTableCache[0].entry;
return true;
}
- if (pTableCache[1].vaddr == page_addr) {
+ if (pTableCache[1].valid && pTableCache[1].vaddr == page_addr) {
entry = pTableCache[1].entry;
return true;
}
- if (pTableCache[2].vaddr == page_addr) {
+ if (pTableCache[2].valid && pTableCache[2].vaddr == page_addr) {
entry = pTableCache[2].entry;
return true;
}
}
bool
-PageTable::translate(Addr vaddr, Addr &paddr)
+PageTableBase::translate(Addr vaddr, Addr &paddr)
{
TheISA::TlbEntry entry;
if (!lookup(vaddr, entry)) {
}
Fault
-PageTable::translate(RequestPtr req)
+PageTableBase::translate(RequestPtr req)
{
Addr paddr;
assert(pageAlign(req->getVaddr() + req->getSize() - 1)
}
void
-PageTable::serialize(std::ostream &os)
+FuncPageTable::serialize(CheckpointOut &cp) const
{
- paramOut(os, "ptable.size", pTable.size());
+ paramOut(cp, "ptable.size", pTable.size());
PTable::size_type count = 0;
+ for (auto &pte : pTable) {
+ ScopedCheckpointSection sec(cp, csprintf("Entry%d", count++));
- PTableItr iter = pTable.begin();
- PTableItr end = pTable.end();
- while (iter != end) {
- os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
-
- paramOut(os, "vaddr", iter->first);
- iter->second.serialize(os);
-
- ++iter;
- ++count;
+ paramOut(cp, "vaddr", pte.first);
+ pte.second.serialize(cp);
}
assert(count == pTable.size());
}
void
-PageTable::unserialize(Checkpoint *cp, const std::string §ion)
+FuncPageTable::unserialize(CheckpointIn &cp)
{
- int i = 0, count;
- paramIn(cp, section, "ptable.size", count);
- Addr vaddr;
- TheISA::TlbEntry *entry;
+ int count;
+ paramIn(cp, "ptable.size", count);
- pTable.clear();
+ for (int i = 0; i < count; ++i) {
+ ScopedCheckpointSection sec(cp, csprintf("Entry%d", i));
- while(i < count) {
- paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
- entry = new TheISA::TlbEntry();
- entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
- pTable[vaddr] = *entry;
- ++i;
- }
+ std::unique_ptr<TheISA::TlbEntry> entry;
+ Addr vaddr;
- process->M5_pid = pTable[vaddr].asn;
+ paramIn(cp, "vaddr", vaddr);
+ entry.reset(new TheISA::TlbEntry());
+ entry->unserialize(cp);
-#if THE_ISA == ALPHA_ISA
- // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work
- // correctly
- int id = process->contextIds[0];
- ThreadContext *tc = process->system->getThreadContext(id);
- tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57);
-#endif
+ pTable[vaddr] = *entry;
+ }
}
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