/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
/**
* @file
- * Definitions of page table.
+ * Definitions of functional page table.
*/
-#include <string>
-#include <map>
#include <fstream>
+#include <map>
+#include <string>
-#include "arch/faults.hh"
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
+#include "debug/MMU.hh"
#include "mem/page_table.hh"
-#include "sim/builder.hh"
+#include "sim/faults.hh"
#include "sim/sim_object.hh"
-#include "sim/system.hh"
using namespace std;
using namespace TheISA;
-PageTable::PageTable(System *_system, Addr _pageSize)
- : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
- system(_system)
+FuncPageTable::FuncPageTable(const std::string &__name, uint64_t _pid, Addr _pageSize)
+ : PageTableBase(__name, _pid, _pageSize)
{
- assert(isPowerOf2(pageSize));
- pTableCache[0].vaddr = 0;
- pTableCache[1].vaddr = 0;
- pTableCache[2].vaddr = 0;
}
-PageTable::~PageTable()
+FuncPageTable::~FuncPageTable()
{
}
-Fault
-PageTable::page_check(Addr addr, int64_t size) const
+void
+FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber)
{
- if (size < sizeof(uint64_t)) {
- if (!isPowerOf2(size)) {
- panic("Invalid request size!\n");
- return genMachineCheckFault();
- }
+ // starting address must be page aligned
+ assert(pageOffset(vaddr) == 0);
- if ((size - 1) & addr)
- return genAlignmentFault();
- }
- else {
- if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
- panic("Invalid request size!\n");
- return genMachineCheckFault();
+ DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
+
+ for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
+ if (!clobber && (pTable.find(vaddr) != pTable.end())) {
+ // already mapped
+ fatal("FuncPageTable::allocate: address 0x%x already mapped", vaddr);
}
- if ((sizeof(uint64_t) - 1) & addr)
- return genAlignmentFault();
+ pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr);
+ eraseCacheEntry(vaddr);
+ updateCache(vaddr, pTable[vaddr]);
}
-
- return NoFault;
}
+void
+FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
+{
+ assert(pageOffset(vaddr) == 0);
+ assert(pageOffset(new_vaddr) == 0);
+ DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
+ new_vaddr, size);
+ for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
+ assert(pTable.find(vaddr) != pTable.end());
+
+ pTable[new_vaddr] = pTable[vaddr];
+ pTable.erase(vaddr);
+ eraseCacheEntry(vaddr);
+ pTable[new_vaddr].updateVaddr(new_vaddr);
+ updateCache(new_vaddr, pTable[new_vaddr]);
+ }
+}
void
-PageTable::allocate(Addr vaddr, int64_t size)
+FuncPageTable::unmap(Addr vaddr, int64_t size)
{
- // starting address must be page aligned
assert(pageOffset(vaddr) == 0);
- DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
+ DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
- m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
-
- if (iter != pTable.end()) {
- // already mapped
- fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
- }
-
- pTable[vaddr] = system->new_page();
- pTableCache[2].paddr = pTableCache[1].paddr;
- pTableCache[2].vaddr = pTableCache[1].vaddr;
- pTableCache[1].paddr = pTableCache[0].paddr;
- pTableCache[1].vaddr = pTableCache[0].vaddr;
- pTableCache[0].paddr = pTable[vaddr];
- pTableCache[0].vaddr = vaddr;
+ assert(pTable.find(vaddr) != pTable.end());
+ pTable.erase(vaddr);
+ eraseCacheEntry(vaddr);
}
+
}
+bool
+FuncPageTable::isUnmapped(Addr vaddr, int64_t size)
+{
+ // starting address must be page aligned
+ assert(pageOffset(vaddr) == 0);
+ for (; size > 0; size -= pageSize, vaddr += pageSize) {
+ if (pTable.find(vaddr) != pTable.end()) {
+ return false;
+ }
+ }
+
+ return true;
+}
bool
-PageTable::translate(Addr vaddr, Addr &paddr)
+FuncPageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
{
Addr page_addr = pageAlign(vaddr);
- paddr = 0;
- if (pTableCache[0].vaddr == vaddr) {
- paddr = pTableCache[0].paddr;
+ if (pTableCache[0].valid && pTableCache[0].vaddr == page_addr) {
+ entry = pTableCache[0].entry;
return true;
}
- if (pTableCache[1].vaddr == vaddr) {
- paddr = pTableCache[1].paddr;
+ if (pTableCache[1].valid && pTableCache[1].vaddr == page_addr) {
+ entry = pTableCache[1].entry;
return true;
}
- if (pTableCache[2].vaddr == vaddr) {
- paddr = pTableCache[2].paddr;
+ if (pTableCache[2].valid && pTableCache[2].vaddr == page_addr) {
+ entry = pTableCache[2].entry;
return true;
}
- m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
+ PTableItr iter = pTable.find(page_addr);
if (iter == pTable.end()) {
return false;
}
- paddr = iter->second + pageOffset(vaddr);
+ updateCache(page_addr, iter->second);
+ entry = iter->second;
return true;
}
+bool
+PageTableBase::translate(Addr vaddr, Addr &paddr)
+{
+ TheISA::TlbEntry entry;
+ if (!lookup(vaddr, entry)) {
+ DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
+ return false;
+ }
+ paddr = pageOffset(vaddr) + entry.pageStart();
+ DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
+ return true;
+}
Fault
-PageTable::translate(RequestPtr &req)
+PageTableBase::translate(RequestPtr req)
{
Addr paddr;
assert(pageAlign(req->getVaddr() + req->getSize() - 1)
== pageAlign(req->getVaddr()));
if (!translate(req->getVaddr(), paddr)) {
- return genPageTableFault(req->getVaddr());
+ return Fault(new GenericPageTableFault(req->getVaddr()));
}
req->setPaddr(paddr);
- return page_check(req->getPaddr(), req->getSize());
+ if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
+ panic("Request spans page boundaries!\n");
+ return NoFault;
+ }
+ return NoFault;
}
void
-PageTable::serialize(std::ostream &os)
+FuncPageTable::serialize(std::ostream &os)
{
paramOut(os, "ptable.size", pTable.size());
- int count = 0;
+ PTable::size_type count = 0;
+
+ PTableItr iter = pTable.begin();
+ PTableItr end = pTable.end();
+ while (iter != end) {
+ os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
+
+ paramOut(os, "vaddr", iter->first);
+ iter->second.serialize(os);
- m5::hash_map<Addr,Addr>::iterator iter;
- m5::hash_map<Addr,Addr>::iterator end;
- for (iter = pTable.begin(); iter != end; ++iter,++count) {
- paramOut(os, csprintf("ptable.entry%dvaddr", count),iter->first);
- paramOut(os, csprintf("ptable.entry%dpaddr", count),iter->second);
+ ++iter;
+ ++count;
}
assert(count == pTable.size());
}
void
-PageTable::unserialize(Checkpoint *cp, const std::string §ion)
+FuncPageTable::unserialize(Checkpoint *cp, const std::string §ion)
{
int i = 0, count;
paramIn(cp, section, "ptable.size", count);
- Addr vaddr, paddr;
pTable.clear();
- while(i < count) {
- paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr);
- paramIn(cp, section, csprintf("ptable.entry%dpaddr", i), paddr);
- pTable[vaddr] = paddr;
- ++i;
- }
+ while (i < count) {
+ TheISA::TlbEntry *entry;
+ Addr vaddr;
+ paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
+ entry = new TheISA::TlbEntry();
+ entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
+ pTable[vaddr] = *entry;
+ delete entry;
+ ++i;
+ }
}
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