Major changes to how SimObjects are created and initialized. Almost all

[gem5.git] / src / mem / page_table.cc

diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 2b460306f7e59c329a673b86ebafbba442d96165..a00d743cd35bebd3f6fbaea49b05332004d72bfd 100644 (file)
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -27,6 +27,7 @@
  *
  * Authors: Steve Reinhardt
  *          Ron Dreslinski
+ *          Ali Saidi
  */
 
 /**
@@ -42,7 +43,6 @@
 #include "base/intmath.hh"
 #include "base/trace.hh"
 #include "mem/page_table.hh"
-#include "sim/builder.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
@@ -89,14 +89,14 @@ PageTable::page_check(Addr addr, int64_t size) const
 }
 
 
-
-
 void
 PageTable::allocate(Addr vaddr, int64_t size)
 {
     // starting address must be page aligned
     assert(pageOffset(vaddr) == 0);
 
+    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
+
     for (; size > 0; size -= pageSize, vaddr += pageSize) {
         m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
 
@@ -106,12 +106,7 @@ PageTable::allocate(Addr vaddr, int64_t size)
         }
 
         pTable[vaddr] = system->new_page();
-        pTableCache[2].paddr = pTableCache[1].paddr;
-        pTableCache[2].vaddr = pTableCache[1].vaddr;
-        pTableCache[1].paddr = pTableCache[0].paddr;
-        pTableCache[1].vaddr = pTableCache[0].vaddr;
-        pTableCache[0].paddr = pTable[vaddr];
-        pTableCache[0].vaddr = vaddr;
+        updateCache(vaddr, pTable[vaddr]);
     }
 }
 
@@ -123,16 +118,16 @@ PageTable::translate(Addr vaddr, Addr &paddr)
     Addr page_addr = pageAlign(vaddr);
     paddr = 0;
 
-    if (pTableCache[0].vaddr == vaddr) {
-        paddr = pTableCache[0].paddr;
+    if (pTableCache[0].vaddr == page_addr) {
+        paddr = pTableCache[0].paddr + pageOffset(vaddr);
         return true;
     }
-    if (pTableCache[1].vaddr == vaddr) {
-        paddr = pTableCache[1].paddr;
+    if (pTableCache[1].vaddr == page_addr) {
+        paddr = pTableCache[1].paddr + pageOffset(vaddr);
         return true;
     }
-    if (pTableCache[2].vaddr == vaddr) {
-        paddr = pTableCache[2].paddr;
+    if (pTableCache[2].vaddr == page_addr) {
+        paddr = pTableCache[2].paddr + pageOffset(vaddr);
         return true;
     }
 
@@ -142,6 +137,7 @@ PageTable::translate(Addr vaddr, Addr &paddr)
         return false;
     }
 
+    updateCache(page_addr, iter->second);
     paddr = iter->second + pageOffset(vaddr);
     return true;
 }
@@ -154,8 +150,46 @@ PageTable::translate(RequestPtr &req)
     assert(pageAlign(req->getVaddr() + req->getSize() - 1)
            == pageAlign(req->getVaddr()));
     if (!translate(req->getVaddr(), paddr)) {
-        return genPageTableFault(req->getVaddr());
+        return Fault(new PageTableFault(req->getVaddr()));
     }
     req->setPaddr(paddr);
     return page_check(req->getPaddr(), req->getSize());
 }
+
+void
+PageTable::serialize(std::ostream &os)
+{
+    paramOut(os, "ptable.size", pTable.size());
+
+    int count = 0;
+
+    m5::hash_map<Addr,Addr>::iterator iter = pTable.begin();
+    m5::hash_map<Addr,Addr>::iterator end = pTable.end();
+    while (iter != end) {
+        paramOut(os, csprintf("ptable.entry%dvaddr", count), iter->first);
+        paramOut(os, csprintf("ptable.entry%dpaddr", count), iter->second);
+
+        ++iter;
+        ++count;
+    }
+    assert(count == pTable.size());
+}
+
+void
+PageTable::unserialize(Checkpoint *cp, const std::string &section)
+{
+    int i = 0, count;
+    paramIn(cp, section, "ptable.size", count);
+    Addr vaddr, paddr;
+
+    pTable.clear();
+
+    while(i < count) {
+        paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr);
+        paramIn(cp, section, csprintf("ptable.entry%dpaddr", i), paddr);
+        pTable[vaddr] = paddr;
+        ++i;
+   }
+
+}
+