mem-cache: Add match functions to QueueEntry

[gem5.git] / src / mem / page_table.hh

diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 470a3e7d6ab9588a81e52d74cad7b6987ebf1e32..447d3a50f94d37bb074f7a5e9d4491d0511c80c2 100644 (file)
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -40,11 +40,8 @@
 #include <string>
 #include <unordered_map>
 
-#include "arch/isa_traits.hh"
-#include "arch/tlb.hh"
 #include "base/intmath.hh"
 #include "base/types.hh"
-#include "config/the_isa.hh"
 #include "mem/request.hh"
 #include "sim/serialize.hh"
 
@@ -52,15 +49,25 @@ class ThreadContext;
 
 class EmulationPageTable : public Serializable
 {
+  public:
+    struct Entry
+    {
+        Addr paddr;
+        uint64_t flags;
+
+        Entry(Addr paddr, uint64_t flags) : paddr(paddr), flags(flags) {}
+        Entry() {}
+    };
+
   protected:
-    typedef std::unordered_map<Addr, TheISA::TlbEntry *> PTable;
+    typedef std::unordered_map<Addr, Entry> PTable;
     typedef PTable::iterator PTableItr;
     PTable pTable;
 
     const Addr pageSize;
     const Addr offsetMask;
 
-    const uint64_t pid;
+    const uint64_t _pid;
     const std::string _name;
 
   public:
@@ -68,24 +75,23 @@ class EmulationPageTable : public Serializable
     EmulationPageTable(
             const std::string &__name, uint64_t _pid, Addr _pageSize) :
             pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
-            pid(_pid), _name(__name)
+            _pid(_pid), _name(__name)
     {
         assert(isPowerOf2(pageSize));
     }
 
-    virtual ~EmulationPageTable();
+    uint64_t pid() const { return _pid; };
+
+    virtual ~EmulationPageTable() {};
 
     /* generic page table mapping flags
      *              unset | set
      * bit 0 - no-clobber | clobber
-     * bit 1 - present    | not-present
      * bit 2 - cacheable  | uncacheable
      * bit 3 - read-write | read-only
      */
     enum MappingFlags : uint32_t {
-        Zero        = 0,
         Clobber     = 1,
-        NotPresent  = 2,
         Uncacheable = 4,
         ReadOnly    = 8,
     };
@@ -123,7 +129,7 @@ class EmulationPageTable : public Serializable
      * @param vaddr The virtual address.
      * @return The page table entry corresponding to vaddr.
      */
-    virtual TheISA::TlbEntry *lookup(Addr vaddr);
+    const Entry *lookup(Addr vaddr);
 
     /**
      * Translate function
@@ -145,7 +151,7 @@ class EmulationPageTable : public Serializable
      * field of req.
      * @param req The memory request.
      */
-    Fault translate(RequestPtr req);
+    Fault translate(const RequestPtr &req);
 
     void getMappings(std::vector<std::pair<Addr, Addr>> *addr_mappings);