/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
*/
/**
* @file
- * Declaration of a non-full system Page Table.
+ * Declarations of a non-full system Page Table.
*/
#ifndef __MEM_PAGE_TABLE_HH__
#define __MEM_PAGE_TABLE_HH__
#include <string>
+#include <unordered_map>
-#include "arch/isa_traits.hh"
-#include "arch/tlb.hh"
-#include "base/hashmap.hh"
+#include "base/bitfield.hh"
+#include "base/intmath.hh"
#include "base/types.hh"
-#include "config/the_isa.hh"
#include "mem/request.hh"
-#include "sim/faults.hh"
#include "sim/serialize.hh"
-class Process;
+class ThreadContext;
-/**
- * Page Table Declaration.
- */
-class PageTable
+class EmulationPageTable : public Serializable
{
- protected:
- typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
- typedef PTable::iterator PTableItr;
- PTable pTable;
+ public:
+ struct Entry
+ {
+ Addr paddr;
+ uint64_t flags;
- struct cacheElement {
- Addr vaddr;
- TheISA::TlbEntry entry;
+ Entry(Addr paddr, uint64_t flags) : paddr(paddr), flags(flags) {}
+ Entry() {}
};
- struct cacheElement pTableCache[3];
+ protected:
+ typedef std::unordered_map<Addr, Entry> PTable;
+ typedef PTable::iterator PTableItr;
+ PTable pTable;
- const Addr pageSize;
+ const Addr _pageSize;
const Addr offsetMask;
- Process *process;
+ const uint64_t _pid;
+ const std::string _name;
public:
- PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
+ EmulationPageTable(
+ const std::string &__name, uint64_t _pid, Addr _pageSize) :
+ _pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
+ _pid(_pid), _name(__name), shared(false)
+ {
+ assert(isPowerOf2(_pageSize));
+ }
+
+ uint64_t pid() const { return _pid; };
- ~PageTable();
+ virtual ~EmulationPageTable() {};
+
+ /* generic page table mapping flags
+ * unset | set
+ * bit 0 - no-clobber | clobber
+ * bit 2 - cacheable | uncacheable
+ * bit 3 - read-write | read-only
+ */
+ enum MappingFlags : uint32_t {
+ Clobber = 1,
+ Uncacheable = 4,
+ ReadOnly = 8,
+ };
+
+ // flag which marks the page table as shared among software threads
+ bool shared;
+
+ virtual void initState() {};
+
+ // for DPRINTF compatibility
+ const std::string name() const { return _name; }
Addr pageAlign(Addr a) { return (a & ~offsetMask); }
Addr pageOffset(Addr a) { return (a & offsetMask); }
+ // Page size can technically vary based on the virtual address, but we'll
+ // ignore that for now.
+ Addr pageSize() { return _pageSize; }
- void allocate(Addr vaddr, int64_t size);
- void remap(Addr vaddr, int64_t size, Addr new_vaddr);
- void deallocate(Addr vaddr, int64_t size);
+ /**
+ * Maps a virtual memory region to a physical memory region.
+ * @param vaddr The starting virtual address of the region.
+ * @param paddr The starting physical address where the region is mapped.
+ * @param size The length of the region.
+ * @param flags Generic mapping flags that can be set by or-ing values
+ * from MappingFlags enum.
+ */
+ virtual void map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags = 0);
+ virtual void remap(Addr vaddr, int64_t size, Addr new_vaddr);
+ virtual void unmap(Addr vaddr, int64_t size);
+
+ /**
+ * Check if any pages in a region are already allocated
+ * @param vaddr The starting virtual address of the region.
+ * @param size The length of the region.
+ * @return True if no pages in the region are mapped.
+ */
+ virtual bool isUnmapped(Addr vaddr, int64_t size);
/**
* Lookup function
* @param vaddr The virtual address.
- * @return entry The page table entry corresponding to vaddr.
+ * @return The page table entry corresponding to vaddr.
*/
- bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
+ const Entry *lookup(Addr vaddr);
/**
* Translate function
* field of req.
* @param req The memory request.
*/
- Fault translate(RequestPtr req);
-
- /**
- * Update the page table cache.
- * @param vaddr virtual address (page aligned) to check
- * @param pte page table entry to return
- */
- inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
- {
- pTableCache[2].entry = pTableCache[1].entry;
- pTableCache[2].vaddr = pTableCache[1].vaddr;
- pTableCache[1].entry = pTableCache[0].entry;
- pTableCache[1].vaddr = pTableCache[0].vaddr;
- pTableCache[0].entry = entry;
- pTableCache[0].vaddr = vaddr;
- }
-
+ Fault translate(const RequestPtr &req);
- void serialize(std::ostream &os);
+ void getMappings(std::vector<std::pair<Addr, Addr>> *addr_mappings);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
#endif // __MEM_PAGE_TABLE_HH__
projects / gem5.git / blobdiff