* Declaration of a non-full system Page Table.
*/
-#ifndef __PAGE_TABLE__
-#define __PAGE_TABLE__
+#ifndef __MEM_PAGE_TABLE_HH__
+#define __MEM_PAGE_TABLE_HH__
#include <string>
-#include "sim/faults.hh"
#include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
#include "base/hashmap.hh"
-#include "base/trace.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
#include "mem/request.hh"
-#include "mem/packet.hh"
-#include "sim/sim_object.hh"
-
-class System;
+#include "sim/serialize.hh"
/**
* Page Table Declaration.
class PageTable
{
protected:
- m5::hash_map<Addr,Addr> pTable;
+ typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
+ typedef PTable::iterator PTableItr;
+ PTable pTable;
struct cacheElement {
- Addr paddr;
Addr vaddr;
- } ;
+ TheISA::TlbEntry entry;
+ };
struct cacheElement pTableCache[3];
const Addr pageSize;
const Addr offsetMask;
- System *system;
+ const uint64_t pid;
+ const std::string _name;
public:
- PageTable(System *_system, Addr _pageSize = TheISA::VMPageSize);
+ PageTable(const std::string &__name, uint64_t _pid,
+ Addr _pageSize = TheISA::VMPageSize);
~PageTable();
+ // for DPRINTF compatibility
+ const std::string name() const { return _name; }
+
Addr pageAlign(Addr a) { return (a & ~offsetMask); }
Addr pageOffset(Addr a) { return (a & offsetMask); }
- Fault page_check(Addr addr, int64_t size) const;
+ void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
+ void remap(Addr vaddr, int64_t size, Addr new_vaddr);
+ void unmap(Addr vaddr, int64_t size);
- void allocate(Addr vaddr, int64_t size);
+ /**
+ * Check if any pages in a region are already allocated
+ * @param vaddr The starting virtual address of the region.
+ * @param size The length of the region.
+ * @return True if no pages in the region are mapped.
+ */
+ bool isUnmapped(Addr vaddr, int64_t size);
+
+ /**
+ * Lookup function
+ * @param vaddr The virtual address.
+ * @return entry The page table entry corresponding to vaddr.
+ */
+ bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
/**
* Translate function
* @param vaddr The virtual address.
- * @return Physical address from translation.
+ * @param paddr Physical address from translation.
+ * @return True if translation exists
*/
bool translate(Addr vaddr, Addr &paddr);
+ /**
+ * Simplified translate function (just check for translation)
+ * @param vaddr The virtual address.
+ * @return True if translation exists
+ */
+ bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
+
/**
* Perform a translation on the memory request, fills in paddr
- * field of mem_req.
+ * field of req.
* @param req The memory request.
*/
- Fault translate(RequestPtr &req);
+ Fault translate(RequestPtr req);
+
+ /**
+ * Update the page table cache.
+ * @param vaddr virtual address (page aligned) to check
+ * @param pte page table entry to return
+ */
+ inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
+ {
+ pTableCache[2].entry = pTableCache[1].entry;
+ pTableCache[2].vaddr = pTableCache[1].vaddr;
+ pTableCache[1].entry = pTableCache[0].entry;
+ pTableCache[1].vaddr = pTableCache[0].vaddr;
+ pTableCache[0].entry = entry;
+ pTableCache[0].vaddr = vaddr;
+ }
+
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
};
-#endif
+#endif // __MEM_PAGE_TABLE_HH__