Make L2+ caches allocate new block for writeback misses

[gem5.git] / src / mem / page_table.hh

diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index fce063280ff98c9e9c49ba630c02ee891b3b9dd9..b8b52174c81380f3e4a1fe010bb0fd6d1a496289 100644 (file)
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -40,13 +40,13 @@
 
 #include "sim/faults.hh"
 #include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
 #include "base/hashmap.hh"
-#include "base/trace.hh"
 #include "mem/request.hh"
-#include "mem/packet.hh"
-#include "sim/sim_object.hh"
+#include "sim/host.hh"
+#include "sim/serialize.hh"
 
-class System;
+class Process;
 
 /**
  * Page Table Declaration.
@@ -54,33 +54,40 @@ class System;
 class PageTable
 {
   protected:
-    m5::hash_map<Addr,Addr> pTable;
+    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
+    typedef PTable::iterator PTableItr;
+    PTable pTable;
 
     struct cacheElement {
-        Addr paddr;
         Addr vaddr;
-    } ;
+        TheISA::TlbEntry entry;
+    };
 
     struct cacheElement pTableCache[3];
 
     const Addr pageSize;
     const Addr offsetMask;
 
-    System *system;
+    Process *process;
 
   public:
 
-    PageTable(System *_system, Addr _pageSize = TheISA::VMPageSize);
+    PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
 
     ~PageTable();
 
     Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
     Addr pageOffset(Addr a) { return (a &  offsetMask); }
 
-    Fault page_check(Addr addr, int64_t size) const;
-
     void allocate(Addr vaddr, int64_t size);
 
+    /**
+     * Lookup function
+     * @param vaddr The virtual address.
+     * @return entry The page table entry corresponding to vaddr.
+     */
+    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
+
     /**
      * Translate function
      * @param vaddr The virtual address.
@@ -90,11 +97,30 @@ class PageTable
 
     /**
      * Perform a translation on the memory request, fills in paddr
-     * field of mem_req.
+     * field of req.
      * @param req The memory request.
      */
-    Fault translate(RequestPtr &req);
+    Fault translate(RequestPtr req);
+
+    /**
+     * Update the page table cache.
+     * @param vaddr virtual address (page aligned) to check
+     * @param pte page table entry to return
+     */
+    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
+    {
+        pTableCache[2].entry = pTableCache[1].entry;
+        pTableCache[2].vaddr = pTableCache[1].vaddr;
+        pTableCache[1].entry = pTableCache[0].entry;
+        pTableCache[1].vaddr = pTableCache[0].vaddr;
+        pTableCache[0].entry = entry;
+        pTableCache[0].vaddr = vaddr;
+    }
+
+
+    void serialize(std::ostream &os);
 
+    void unserialize(Checkpoint *cp, const std::string &section);
 };
 
 #endif