mem: Add a method for setting the time on a packet.

[gem5.git] / src / mem / page_table.hh

diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index f7212d42311a1616e8e5f90bb8d6d88b9bf0320b..b8b52174c81380f3e4a1fe010bb0fd6d1a496289 100644 (file)
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -37,41 +37,56 @@
 #define __PAGE_TABLE__
 
 #include <string>
-#include <map>
 
+#include "sim/faults.hh"
 #include "arch/isa_traits.hh"
-#include "base/trace.hh"
+#include "arch/tlb.hh"
+#include "base/hashmap.hh"
 #include "mem/request.hh"
-#include "mem/packet.hh"
-#include "sim/sim_object.hh"
+#include "sim/host.hh"
+#include "sim/serialize.hh"
 
-class System;
+class Process;
 
 /**
- * Page Table Decleration.
+ * Page Table Declaration.
  */
 class PageTable
 {
   protected:
-    std::map<Addr,Addr> pTable;
+    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
+    typedef PTable::iterator PTableItr;
+    PTable pTable;
+
+    struct cacheElement {
+        Addr vaddr;
+        TheISA::TlbEntry entry;
+    };
+
+    struct cacheElement pTableCache[3];
 
     const Addr pageSize;
     const Addr offsetMask;
 
-    System *system;
+    Process *process;
 
   public:
 
-    PageTable(System *_system, Addr _pageSize = TheISA::VMPageSize);
+    PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
 
     ~PageTable();
 
     Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
     Addr pageOffset(Addr a) { return (a &  offsetMask); }
 
-    Fault page_check(Addr addr, int size) const;
+    void allocate(Addr vaddr, int64_t size);
 
-    void allocate(Addr vaddr, int size);
+    /**
+     * Lookup function
+     * @param vaddr The virtual address.
+     * @return entry The page table entry corresponding to vaddr.
+     */
+    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
 
     /**
      * Translate function
@@ -82,11 +97,30 @@ class PageTable
 
     /**
      * Perform a translation on the memory request, fills in paddr
-     * field of mem_req.
+     * field of req.
      * @param req The memory request.
      */
-    Fault translate(RequestPtr &req);
+    Fault translate(RequestPtr req);
+
+    /**
+     * Update the page table cache.
+     * @param vaddr virtual address (page aligned) to check
+     * @param pte page table entry to return
+     */
+    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
+    {
+        pTableCache[2].entry = pTableCache[1].entry;
+        pTableCache[2].vaddr = pTableCache[1].vaddr;
+        pTableCache[1].entry = pTableCache[0].entry;
+        pTableCache[1].vaddr = pTableCache[0].vaddr;
+        pTableCache[0].entry = entry;
+        pTableCache[0].vaddr = vaddr;
+    }
+
+
+    void serialize(std::ostream &os);
 
+    void unserialize(Checkpoint *cp, const std::string &section);
 };
 
 #endif