//
class PhysicalMemory : public MemObject
{
+ protected:
+
class MemoryPort : public SimpleTimingPort
{
PhysicalMemory *memory;
virtual void getDeviceAddressRanges(AddrRangeList &resp,
bool &snoop);
- virtual int deviceBlockSize();
+ virtual unsigned deviceBlockSize() const;
};
int numPorts;
contextId(req->contextId())
{
}
+ // constructor for unserialization use
+ LockedAddr(Addr _addr, int _cid)
+ : addr(_addr), contextId(_cid)
+ {
+ }
};
std::list<LockedAddr> lockedAddrList;
Request *req = pkt->req;
if (lockedAddrList.empty()) {
// no locked addrs: nothing to check, store_conditional fails
- bool isLlsc = pkt->isLlsc();
- if (isLlsc) {
+ bool isLLSC = pkt->isLLSC();
+ if (isLLSC) {
req->setExtraData(0);
}
- return !isLlsc; // only do write if not an sc
+ return !isLLSC; // only do write if not an sc
} else {
// iterate over list...
return checkLockedAddrList(pkt);
}
uint8_t *pmemAddr;
- int pagePtr;
Tick lat;
Tick lat_var;
std::vector<MemoryPort*> ports;
typedef std::vector<MemoryPort*>::iterator PortIterator;
- uint64_t cachedSize;
- uint64_t cachedStart;
+ uint64_t _size;
+ uint64_t _start;
public:
- Addr new_page();
- uint64_t size() { return cachedSize; }
- uint64_t start() { return cachedStart; }
+ uint64_t size() { return _size; }
+ uint64_t start() { return _start; }
public:
typedef PhysicalMemoryParams Params;
}
public:
- int deviceBlockSize();
+ unsigned deviceBlockSize() const;
void getAddressRanges(AddrRangeList &resp, bool &snoop);
virtual Port *getPort(const std::string &if_name, int idx = -1);
void virtual init();