//
class PhysicalMemory : public MemObject
{
+ protected:
+
class MemoryPort : public SimpleTimingPort
{
PhysicalMemory *memory;
virtual void getDeviceAddressRanges(AddrRangeList &resp,
bool &snoop);
- virtual int deviceBlockSize();
+ virtual unsigned deviceBlockSize() const;
};
int numPorts;
static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
- Addr addr; // locked address
- int cpuNum; // locking CPU
- int threadNum; // locking thread ID within CPU
+ Addr addr; // locked address
+ int contextId; // locking hw context
// check for matching execution context
bool matchesContext(Request *req)
{
- return (cpuNum == req->getCpuNum() &&
- threadNum == req->getThreadNum());
+ return (contextId == req->contextId());
}
LockedAddr(Request *req)
: addr(mask(req->getPaddr())),
- cpuNum(req->getCpuNum()),
- threadNum(req->getThreadNum())
+ contextId(req->contextId())
+ {
+ }
+ // constructor for unserialization use
+ LockedAddr(Addr _addr, int _cid)
+ : addr(_addr), contextId(_cid)
{
}
};
// inline a quick check for an empty locked addr list (hopefully
// the common case), and do the full list search (if necessary) in
// this out-of-line function
- bool checkLockedAddrList(Request *req);
+ bool checkLockedAddrList(PacketPtr pkt);
// Record the address of a load-locked operation so that we can
// clear the execution context's lock flag if a matching store is
// performed
- void trackLoadLocked(Request *req);
+ void trackLoadLocked(PacketPtr pkt);
// Compare a store address with any locked addresses so we can
// clear the lock flag appropriately. Return value set to 'false'
// requesting execution context), 'true' otherwise. Note that
// this method must be called on *all* stores since even
// non-conditional stores must clear any matching lock addresses.
- bool writeOK(Request *req) {
+ bool writeOK(PacketPtr pkt) {
+ Request *req = pkt->req;
if (lockedAddrList.empty()) {
// no locked addrs: nothing to check, store_conditional fails
- bool isLocked = req->isLocked();
- if (isLocked) {
+ bool isLLSC = pkt->isLLSC();
+ if (isLLSC) {
req->setExtraData(0);
}
- return !isLocked; // only do write if not an sc
+ return !isLLSC; // only do write if not an sc
} else {
// iterate over list...
- return checkLockedAddrList(req);
+ return checkLockedAddrList(pkt);
}
}
uint8_t *pmemAddr;
- int pagePtr;
Tick lat;
+ Tick lat_var;
std::vector<MemoryPort*> ports;
typedef std::vector<MemoryPort*>::iterator PortIterator;
+ uint64_t _size;
+ uint64_t _start;
public:
- Addr new_page();
- uint64_t size() { return params()->range.size(); }
- uint64_t start() { return params()->range.start; }
+ uint64_t size() { return _size; }
+ uint64_t start() { return _start; }
public:
typedef PhysicalMemoryParams Params;
}
public:
- int deviceBlockSize();
+ unsigned deviceBlockSize() const;
void getAddressRanges(AddrRangeList &resp, bool &snoop);
virtual Port *getPort(const std::string &if_name, int idx = -1);
void virtual init();
unsigned int drain(Event *de);
protected:
+ Tick doAtomicAccess(PacketPtr pkt);
void doFunctionalAccess(PacketPtr pkt);
virtual Tick calculateLatency(PacketPtr pkt);
void recvStatusChange(Port::Status status);