SLICC: Remove WakeUp* import calls from ast/__init__.py

[gem5.git] / src / mem / physical.hh

diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index f7200b50208dabf694abfc8052aaecfb38154873..cd6d809e240dd9a6c265b4cc3ee38dec1cb4e7dc 100644 (file)
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -34,19 +34,23 @@
 #ifndef __PHYSICAL_MEMORY_HH__
 #define __PHYSICAL_MEMORY_HH__
 
+#include <map>
+#include <string>
+
 #include "base/range.hh"
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/tport.hh"
+#include "params/PhysicalMemory.hh"
 #include "sim/eventq.hh"
-#include <map>
-#include <string>
 
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
 //
 class PhysicalMemory : public MemObject
 {
+  protected:
+
     class MemoryPort : public SimpleTimingPort
     {
         PhysicalMemory *memory;
@@ -64,9 +68,9 @@ class PhysicalMemory : public MemObject
         virtual void recvStatusChange(Status status);
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
-                                            AddrRangeList &snoop);
+                                            bool &snoop);
 
-        virtual int deviceBlockSize();
+        virtual unsigned deviceBlockSize() const;
     };
 
     int numPorts;
@@ -87,21 +91,23 @@ class PhysicalMemory : public MemObject
 
         static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
 
-        Addr addr;     // locked address
-        int cpuNum;    // locking CPU
-        int threadNum; // locking thread ID within CPU
+        Addr addr;      // locked address
+        int contextId;     // locking hw context
 
         // check for matching execution context
         bool matchesContext(Request *req)
         {
-            return (cpuNum == req->getCpuNum() &&
-                    threadNum == req->getThreadNum());
+            return (contextId == req->contextId());
         }
 
         LockedAddr(Request *req)
             : addr(mask(req->getPaddr())),
-              cpuNum(req->getCpuNum()),
-              threadNum(req->getThreadNum())
+              contextId(req->contextId())
+        {
+        }
+        // constructor for unserialization use
+        LockedAddr(Addr _addr, int _cid)
+            : addr(_addr), contextId(_cid)
         {
         }
     };
@@ -112,12 +118,12 @@ class PhysicalMemory : public MemObject
     // inline a quick check for an empty locked addr list (hopefully
     // the common case), and do the full list search (if necessary) in
     // this out-of-line function
-    bool checkLockedAddrList(Request *req);
+    bool checkLockedAddrList(PacketPtr pkt);
 
     // Record the address of a load-locked operation so that we can
     // clear the execution context's lock flag if a matching store is
     // performed
-    void trackLoadLocked(Request *req);
+    void trackLoadLocked(PacketPtr pkt);
 
     // Compare a store address with any locked addresses so we can
     // clear the lock flag appropriately.  Return value set to 'false'
@@ -126,54 +132,53 @@ class PhysicalMemory : public MemObject
     // requesting execution context), 'true' otherwise.  Note that
     // this method must be called on *all* stores since even
     // non-conditional stores must clear any matching lock addresses.
-    bool writeOK(Request *req) {
+    bool writeOK(PacketPtr pkt) {
+        Request *req = pkt->req;
         if (lockedAddrList.empty()) {
             // no locked addrs: nothing to check, store_conditional fails
-            bool isLocked = req->isLocked();
-            if (isLocked) {
+            bool isLLSC = pkt->isLLSC();
+            if (isLLSC) {
                 req->setExtraData(0);
             }
-            return !isLocked; // only do write if not an sc
+            return !isLLSC; // only do write if not an sc
         } else {
             // iterate over list...
-            return checkLockedAddrList(req);
+            return checkLockedAddrList(pkt);
         }
     }
 
     uint8_t *pmemAddr;
-    MemoryPort *port;
-    int pagePtr;
     Tick lat;
+    Tick lat_var;
+    std::vector<MemoryPort*> ports;
+    typedef std::vector<MemoryPort*>::iterator PortIterator;
 
+    uint64_t _size;
+    uint64_t _start;
   public:
-    Addr new_page();
-    uint64_t size() { return params()->addrRange.size(); }
-    uint64_t start() { return params()->addrRange.start; }
-
-    struct Params
-    {
-        std::string name;
-        Range<Addr> addrRange;
-        Tick latency;
-        bool zero;
-    };
-
-  protected:
-    Params *_params;
+    uint64_t size() { return _size; }
+    uint64_t start() { return _start; }
 
   public:
-    const Params *params() const { return _params; }
-    PhysicalMemory(Params *p);
+    typedef PhysicalMemoryParams Params;
+    PhysicalMemory(const Params *p);
     virtual ~PhysicalMemory();
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
   public:
-    int deviceBlockSize();
-    void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
+    unsigned deviceBlockSize() const;
+    void getAddressRanges(AddrRangeList &resp, bool &snoop);
     virtual Port *getPort(const std::string &if_name, int idx = -1);
     void virtual init();
     unsigned int drain(Event *de);
 
   protected:
+    Tick doAtomicAccess(PacketPtr pkt);
     void doFunctionalAccess(PacketPtr pkt);
     virtual Tick calculateLatency(PacketPtr pkt);
     void recvStatusChange(Port::Status status);