mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / port.hh

diff --git a/src/mem/port.hh b/src/mem/port.hh
index 0d88441dc0d6efcaaf60c9cb9a1d93a4382436ab..39f6dead894a3f1f8331ebe9624d8c06795f4b99 100644 (file)
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012,2015 ARM Limited
+ * Copyright (c) 2011-2012,2015,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -223,6 +223,19 @@ class MasterPort : public BaseMasterPort
     */
     bool sendTimingReq(PacketPtr pkt);
 
+    /**
+     * Check if the slave can handle a timing request.
+     *
+     * If the send cannot be handled at the moment, as indicated by
+     * the return value, then the sender will receive a recvReqRetry
+     * at which point it can re-issue a sendTimingReq.
+     *
+     * @param pkt Packet to send.
+     *
+     * @return If the send was succesful or not.
+     */
+    bool tryTiming(PacketPtr pkt) const;
+
     /**
      * Attempt to send a timing snoop response packet to the slave
      * port by calling its corresponding receive function. If the send
@@ -451,6 +464,13 @@ class SlavePort : public BaseSlavePort
      */
     virtual bool recvTimingReq(PacketPtr pkt) = 0;
 
+    /**
+     * Availability request from the master port.
+     */
+    virtual bool tryTiming(PacketPtr pkt) {
+        panic("%s was not expecting a %s\n", name(), __func__);
+    }
+
     /**
      * Receive a timing snoop response from the master port.
      */