Make L2+ caches allocate new block for writeback misses

[gem5.git] / src / mem / port_impl.hh

diff --git a/src/mem/port_impl.hh b/src/mem/port_impl.hh
index e9a159293b08681341f59cb48affcc7a1ea0e0d3..989cfd338398c74d87eb1108e67dcc400932e932 100644 (file)
--- a/src/mem/port_impl.hh
+++ b/src/mem/port_impl.hh
@@ -28,8 +28,9 @@
  * Authors: Ali Saidi
  */
 
-#include "arch/isa_specific.hh"
+//To get endianness
 #include "arch/isa_traits.hh"
+
 #include "mem/port.hh"
 #include "sim/byteswap.hh"