Ruby: Add support for functional accesses

[gem5.git] / src / mem / protocol / MESI_CMP_directory-dma.sm

diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm
index 143c465efc16e6e4bdf598b4ebb1405c8976f9d8..f32c73218fcf250a3c881896e3698a9723b86008 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm
@@ -1,15 +1,16 @@
 
 machine(DMA, "DMA Controller") 
-: int request_latency
+: DMASequencer * dma_sequencer,
+  int request_latency = 6
 {
 
-  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
-  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
+  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
+  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
 
-  enumeration(State, desc="DMA states", default="DMA_State_READY") {
-    READY, desc="Ready to accept a new request";
-    BUSY_RD,  desc="Busy: currently processing a request";
-    BUSY_WR,  desc="Busy: currently processing a request";
+  state_declaration(State, desc="DMA states", default="DMA_State_READY") {
+    READY, AccessPermission:Invalid, desc="Ready to accept a new request";
+    BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
+    BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
   }
 
   enumeration(Event, desc="DMA events") {
@@ -19,13 +20,12 @@ machine(DMA, "DMA Controller")
     Ack,          desc="DMA write to memory completed";
   }
 
-  external_type(DMASequencer) {
+  structure(DMASequencer, external="yes") {
     void ackCallback();
     void dataCallback(DataBlock);
   }
 
   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
   State cur_state, no_vector="true";
 
   State getState(Address addr) {
@@ -35,7 +35,18 @@ machine(DMA, "DMA Controller")
   cur_state := state;
   }
 
-  out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
+  DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+    error("DMA does not support get data block.");
+  }
+
+  out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
 
   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
     if (dmaRequestQueue_in.isReady()) {