ruby: reverts to changeset: bf82f1f7b040

[gem5.git] / src / mem / protocol / MESI_Three_Level-L0cache.sm

diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index fb9e762daff66e59f4496508fe1ca2fc278cfa99..8e44766ea052c352426b3fc7e50d4ea6b56a99f7 100644 (file)
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -145,22 +145,22 @@ machine(L0Cache, "MESI Directory L0 Cache")
 
   // inclusive cache returns L0 entries only
   Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
-    Entry Dcache_entry := static_cast(Entry, "pointer", Dcache.lookup(addr));
+    Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
     if(is_valid(Dcache_entry)) {
       return Dcache_entry;
     }
 
-    Entry Icache_entry := static_cast(Entry, "pointer", Icache.lookup(addr));
+    Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
     return Icache_entry;
   }
 
   Entry getDCacheEntry(Addr addr), return_by_pointer="yes" {
-    Entry Dcache_entry := static_cast(Entry, "pointer", Dcache.lookup(addr));
+    Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
     return Dcache_entry;
   }
 
   Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
-    Entry Icache_entry := static_cast(Entry, "pointer", Icache.lookup(addr));
+    Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
     return Icache_entry;
   }
 
@@ -189,7 +189,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
   }
 
   AccessPermission getAccessPermission(Addr addr) {
-    TBE tbe := TBEs.lookup(addr);
+    TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState));
       return L0Cache_State_to_permission(tbe.TBEState);
@@ -206,7 +206,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
   }
 
   void functionalRead(Addr addr, Packet *pkt) {
-    TBE tbe := TBEs.lookup(addr);
+    TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt);
     } else {
@@ -217,7 +217,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
   int functionalWrite(Addr addr, Packet *pkt) {
     int num_functional_writes := 0;
 
-    TBE tbe := TBEs.lookup(addr);
+    TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
         testAndWrite(addr, tbe.DataBlk, pkt);
@@ -260,7 +260,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
         assert(in_msg.Dest == machineID);
 
         Entry cache_entry := getCacheEntry(in_msg.addr);
-        TBE tbe := TBEs.lookup(in_msg.addr);
+        TBE tbe := TBEs[in_msg.addr];
 
         if(in_msg.Class == CoherenceClass:DATA_EXCLUSIVE) {
             trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
@@ -301,7 +301,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
           if (is_valid(Icache_entry)) {
             // The tag matches for the L0, so the L0 asks the L2 for it.
             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                    Icache_entry, TBEs.lookup(in_msg.LineAddress));
+                    Icache_entry, TBEs[in_msg.LineAddress]);
           } else {
 
             // Check to see if it is in the OTHER L0
@@ -309,19 +309,19 @@ machine(L0Cache, "MESI Directory L0 Cache")
             if (is_valid(Dcache_entry)) {
               // The block is in the wrong L0, put the request on the queue to the shared L2
               trigger(Event:L0_Replacement, in_msg.LineAddress,
-                      Dcache_entry, TBEs.lookup(in_msg.LineAddress));
+                      Dcache_entry, TBEs[in_msg.LineAddress]);
             }
 
             if (Icache.cacheAvail(in_msg.LineAddress)) {
               // L0 does't have the line, but we have space for it
               // in the L0 so let's see if the L2 has it
               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                      Icache_entry, TBEs.lookup(in_msg.LineAddress));
+                      Icache_entry, TBEs[in_msg.LineAddress]);
             } else {
               // No room in the L0, so we need to make room in the L0
               trigger(Event:L0_Replacement, Icache.cacheProbe(in_msg.LineAddress),
                       getICacheEntry(Icache.cacheProbe(in_msg.LineAddress)),
-                      TBEs.lookup(Icache.cacheProbe(in_msg.LineAddress)));
+                      TBEs[Icache.cacheProbe(in_msg.LineAddress)]);
             }
           }
         } else {
@@ -331,7 +331,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
           if (is_valid(Dcache_entry)) {
             // The tag matches for the L0, so the L0 ask the L1 for it
             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                    Dcache_entry, TBEs.lookup(in_msg.LineAddress));
+                    Dcache_entry, TBEs[in_msg.LineAddress]);
           } else {
 
             // Check to see if it is in the OTHER L0
@@ -339,19 +339,19 @@ machine(L0Cache, "MESI Directory L0 Cache")
             if (is_valid(Icache_entry)) {
               // The block is in the wrong L0, put the request on the queue to the private L1
               trigger(Event:L0_Replacement, in_msg.LineAddress,
-                      Icache_entry, TBEs.lookup(in_msg.LineAddress));
+                      Icache_entry, TBEs[in_msg.LineAddress]);
             }
 
             if (Dcache.cacheAvail(in_msg.LineAddress)) {
               // L1 does't have the line, but we have space for it
               // in the L0 let's see if the L1 has it
               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                      Dcache_entry, TBEs.lookup(in_msg.LineAddress));
+                      Dcache_entry, TBEs[in_msg.LineAddress]);
             } else {
               // No room in the L1, so we need to make room in the L0
               trigger(Event:L0_Replacement, Dcache.cacheProbe(in_msg.LineAddress),
                       getDCacheEntry(Dcache.cacheProbe(in_msg.LineAddress)),
-                      TBEs.lookup(Dcache.cacheProbe(in_msg.LineAddress)));
+                      TBEs[Dcache.cacheProbe(in_msg.LineAddress)]);
             }
           }
         }
@@ -459,38 +459,21 @@ machine(L0Cache, "MESI Directory L0 Cache")
     }
   }
 
-  action(h_load_hit, "hd", desc="If not prefetch, notify sequencer the load completed.") {
+  action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
     assert(is_valid(cache_entry));
     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    Dcache.setMRU(cache_entry);
     sequencer.readCallback(address, cache_entry.DataBlk);
   }
 
-  action(h_ifetch_hit, "hi", desc="If not prefetch, notify sequencer the ifetch completed.") {
+  action(hx_load_hit, "hx", desc="If not prefetch, notify sequencer the load completed.") {
     assert(is_valid(cache_entry));
     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    Icache.setMRU(cache_entry);
-    sequencer.readCallback(address, cache_entry.DataBlk);
-  }
-
-  action(hx_load_hit, "hxd", desc="notify sequencer the load completed.") {
-    assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    Dcache.setMRU(cache_entry);
-    sequencer.readCallback(address, cache_entry.DataBlk, true);
-  }
-
-  action(hx_ifetch_hit, "hxi", desc="notify sequencer the ifetch completed.") {
-    assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    Icache.setMRU(cache_entry);
     sequencer.readCallback(address, cache_entry.DataBlk, true);
   }
 
   action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
     assert(is_valid(cache_entry));
     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    Dcache.setMRU(cache_entry);
     sequencer.writeCallback(address, cache_entry.DataBlk);
     cache_entry.Dirty := true;
   }
@@ -498,7 +481,6 @@ machine(L0Cache, "MESI Directory L0 Cache")
   action(hhx_store_hit, "\hx", desc="If not prefetch, notify sequencer that store completed.") {
     assert(is_valid(cache_entry));
     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
-    Dcache.setMRU(cache_entry);
     sequencer.writeCallback(address, cache_entry.DataBlk, true);
     cache_entry.Dirty := true;
   }
@@ -507,7 +489,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
     check_allocate(TBEs);
     assert(is_valid(cache_entry));
     TBEs.allocate(address);
-    set_tbe(TBEs.lookup(address));
+    set_tbe(TBEs[address]);
     tbe.Dirty := cache_entry.Dirty;
     tbe.DataBlk := cache_entry.DataBlk;
   }
@@ -643,7 +625,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
   }
 
   transition({S,E,M}, Ifetch) {
-    h_ifetch_hit;
+    h_load_hit;
     uu_profileInstHit;
     k_popMandatoryQueue;
   }
@@ -730,7 +712,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
 
   transition(Inst_IS, Data, S) {
     u_writeInstToCache;
-    hx_ifetch_hit;
+    hx_load_hit;
     s_deallocateTBE;
     o_popIncomingResponseQueue;
     kd_wakeUpDependents;
@@ -738,7 +720,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
 
   transition(Inst_IS, Data_Exclusive, E) {
     u_writeInstToCache;
-    hx_ifetch_hit;
+    hx_load_hit;
     s_deallocateTBE;
     o_popIncomingResponseQueue;
     kd_wakeUpDependents;