cpu: Add TraceCPU to playback elastic traces

[gem5.git] / src / mem / protocol / MESI_Three_Level-msg.sm

diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/protocol/MESI_Three_Level-msg.sm
index 7f32f1bcd30ede5eab295379f4c5d3c2d919922c..7fe4add462aa4bc323963f3b8f23da9c5c4b89ab 100644 (file)
--- a/src/mem/protocol/MESI_Three_Level-msg.sm
+++ b/src/mem/protocol/MESI_Three_Level-msg.sm
@@ -50,7 +50,7 @@ enumeration(CoherenceClass, desc="...") {
 
 // Class for messages sent between the L0 and the L1 controllers.
 structure(CoherenceMsg, desc="...", interface="Message") {
-  Address addr,              desc="Physical address of the cache block";
+  Addr addr,              desc="Physical address of the cache block";
   CoherenceClass Class,         desc="Type of message (GetS, GetX, PutX, etc)";
   RubyAccessMode AccessMode,    desc="user/supervisor access type";
   MachineID Sender,             desc="What component sent this message";