* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "MESI Directory L2 Cache CMP")
+machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")
: CacheMemory * L2cache;
Cycles l2_request_latency := 2;
Cycles l2_response_latency := 2;
// Message Queues
// From local bank of L2 cache TO the network
MessageBuffer * DirRequestFromL2Cache, network="To", virtual_network="0",
- ordered="false", vnet_type="request"; // this L2 bank -> Memory
+ vnet_type="request"; // this L2 bank -> Memory
MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="2",
- ordered="false", vnet_type="request"; // this L2 bank -> a local L1
+ vnet_type="request"; // this L2 bank -> a local L1
MessageBuffer * responseFromL2Cache, network="To", virtual_network="1",
- ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || Memory
+ vnet_type="response"; // this L2 bank -> a local L1 || Memory
// FROM the network to this local bank of L2 cache
MessageBuffer * unblockToL2Cache, network="From", virtual_network="2",
- ordered="false", vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
+ vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0",
- ordered="false", vnet_type="request"; // a local L1 -> this L2 bank
+ vnet_type="request"; // a local L1 -> this L2 bank
MessageBuffer * responseToL2Cache, network="From", virtual_network="1",
- ordered="false", vnet_type="response"; // a local L1 || Memory -> this L2 bank
+ vnet_type="response"; // a local L1 || Memory -> this L2 bank
{
// STATES
state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
// TBE fields
structure(TBE, desc="...") {
- Address Addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="Data is Dirty";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+ Tick clockEdge();
+ Tick cyclesToTicks(Cycles c);
+ Cycles ticksToCycles(Tick t);
+
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
- void wakeUpBuffers(Address a);
+ void wakeUpBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
+ MachineID mapAddressToMachine(Addr addr, MachineType mtype);
// inclusive cache, returns L2 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
return static_cast(Entry, "pointer", L2cache[addr]);
}
- bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
+ bool isSharer(Addr addr, MachineID requestor, Entry cache_entry) {
if (is_valid(cache_entry)) {
return cache_entry.Sharers.isElement(requestor);
} else {
}
}
- void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
+ void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
+ DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %#x\n",
machineID, requestor, addr);
cache_entry.Sharers.add(requestor);
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if(is_valid(tbe)) {
return tbe.TBEState;
} else if (is_valid(cache_entry)) {
return State:NP;
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
// MUST CHANGE
if (is_valid(tbe)) {
tbe.TBEState := state;
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
return num_functional_writes;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L2Cache_State_to_permission(state));
}
}
- Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
+ Event L1Cache_request_type_to_event(CoherenceRequestType type, Addr addr,
MachineID requestor, Entry cache_entry) {
if(type == CoherenceRequestType:GETS) {
return Event:L1_GETS;
return Event:L1_PUTX_old;
}
} else {
- DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
+ DPRINTF(RubySlicc, "address: %#x, Request Type: %s\n", addr, type);
error("Invalid L1 forwarded request type");
}
}
in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
- if(L1unblockNetwork_in.isReady()) {
+ if(L1unblockNetwork_in.isReady(clockEdge())) {
peek(L1unblockNetwork_in, ResponseMsg) {
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
- DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
- in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
+ Entry cache_entry := getCacheEntry(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
+ DPRINTF(RubySlicc, "Addr: %#x State: %s Sender: %s Type: %s Dest: %s\n",
+ in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Sender, in_msg.Type, in_msg.Destination);
assert(in_msg.Destination.isElement(machineID));
if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
- trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Exclusive_Unblock, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
- trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Unblock, in_msg.addr, cache_entry, tbe);
} else {
error("unknown unblock message");
}
// Response L2 Network - response msg to this particular L2 bank
in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
- if (responseL2Network_in.isReady()) {
+ if (responseL2Network_in.isReady(clockEdge())) {
peek(responseL2Network_in, ResponseMsg) {
// test wether it's from a local L1 or an off chip source
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
+ Entry cache_entry := getCacheEntry(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
if(in_msg.Type == CoherenceResponseType:DATA) {
if (in_msg.Dirty) {
- trigger(Event:WB_Data, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:WB_Data, in_msg.addr, cache_entry, tbe);
} else {
- trigger(Event:WB_Data_clean, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:WB_Data_clean, in_msg.addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceResponseType:ACK) {
if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
- trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Ack_all, in_msg.addr, cache_entry, tbe);
} else {
- trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
}
} else {
error("unknown message type");
} else { // external message
if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
- trigger(Event:Mem_Data, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Mem_Data, in_msg.addr, cache_entry, tbe);
} else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
- trigger(Event:Mem_Ack, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:Mem_Ack, in_msg.addr, cache_entry, tbe);
} else if(in_msg.Type == CoherenceResponseType:INV) {
- trigger(Event:MEM_Inv, in_msg.Addr, cache_entry, tbe);
+ trigger(Event:MEM_Inv, in_msg.addr, cache_entry, tbe);
} else {
error("unknown message type");
}
// L1 Request
in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
- if(L1RequestL2Network_in.isReady()) {
+ if(L1RequestL2Network_in.isReady(clockEdge())) {
peek(L1RequestL2Network_in, RequestMsg) {
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
+ Entry cache_entry := getCacheEntry(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
- DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
- in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
+ DPRINTF(RubySlicc, "Addr: %#x State: %s Req: %s Type: %s Dest: %s\n",
+ in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Requestor, in_msg.Type, in_msg.Destination);
assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
if (is_valid(cache_entry)) {
// The L2 contains the block, so proceeded with handling the request
- trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
+ trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr,
in_msg.Requestor, cache_entry),
- in_msg.Addr, cache_entry, tbe);
+ in_msg.addr, cache_entry, tbe);
} else {
- if (L2cache.cacheAvail(in_msg.Addr)) {
+ if (L2cache.cacheAvail(in_msg.addr)) {
// L2 does't have the line, but we have space for it in the L2
- trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
+ trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr,
in_msg.Requestor, cache_entry),
- in_msg.Addr, cache_entry, tbe);
+ in_msg.addr, cache_entry, tbe);
} else {
// No room in the L2, so we need to make room before handling the request
- Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr));
+ Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.addr));
if (isDirty(L2cache_entry)) {
- trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
- L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.Addr)]);
+ trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.addr),
+ L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]);
} else {
- trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr),
- L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.Addr)]);
+ trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.addr),
+ L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]);
}
}
}
action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
out_msg.MessageSize := MessageSizeType:Control;
}
}
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := in_msg.Type;
out_msg.Requestor := in_msg.Requestor;
out_msg.Destination.add(cache_entry.Exclusive);
action(c_exclusiveReplacement, "c", desc="Send data to memory") {
enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
out_msg.Sender := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
out_msg.MessageSize := MessageSizeType:Response_Control;
}
}
action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(tbe));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
out_msg.Sender := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
assert(tbe.L1_GetS_IDs.count() > 0);
enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
assert(tbe.L1_GetS_IDs.count() == 1);
enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(tbe));
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(tbe.L1_GetX_ID);
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
out_msg.DataBlk := cache_entry.DataBlk;
- DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
- out_msg.Addr, out_msg.Destination, out_msg.DataBlk);
+ DPRINTF(RubySlicc, "Address: %#x, Destination: %s, DataBlock: %s\n",
+ out_msg.addr, out_msg.Destination, out_msg.DataBlk);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:INV;
out_msg.Requestor := machineID;
out_msg.Destination := cache_entry.Sharers;
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:INV;
out_msg.Requestor := in_msg.Requestor;
out_msg.Destination := cache_entry.Sharers;
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceRequestType:INV;
out_msg.Requestor := in_msg.Requestor;
out_msg.Destination := cache_entry.Sharers;
}
action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
- profileMsgDelay(0, L1RequestL2Network_in.dequeue());
+ Tick delay := L1RequestL2Network_in.dequeue(clockEdge());
+ profileMsgDelay(0, ticksToCycles(delay));
}
action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
- profileMsgDelay(0, L1unblockNetwork_in.dequeue());
+ Tick delay := L1unblockNetwork_in.dequeue(clockEdge());
+ profileMsgDelay(0, ticksToCycles(delay));
}
action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
- profileMsgDelay(1, responseL2Network_in.dequeue());
+ Tick delay := responseL2Network_in.dequeue(clockEdge());
+ profileMsgDelay(1, ticksToCycles(delay));
}
action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
action(t_sendWBAck, "t", desc="Send writeback ACK") {
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:WB_ACK;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
peek(L1RequestL2Network_in, RequestMsg) {
enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(cache_entry));
- out_msg.Addr := address;
+ out_msg.addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
}
action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
- responseL2Network_in.recycle();
+ responseL2Network_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
}
action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
projects / gem5.git / blobdiff